CY28158 Cypress Semiconductor Corporation., CY28158 Datasheet

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CY28158

Manufacturer Part Number
CY28158
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-07039 Rev. *B
Features
• Maximized EMI suppression using Cypress’s spread
• Based on Industry Standard CK133 Pinout with all out-
• 0.5% downspread outputs deliver up to 10dB lower EMI
• 6 skew-controlled copies of CPU output
• 6 copies of PCI output (synchronous w/CPU output)
• 2 copies of 66 MHz fixed frequency 3.3V clock
• 3 copies of 16.67 MHz IOAPIC clock, synchronous to
• 1 copy of 48 MHz USB output
• 2 copies of 14.31818 MHz reference clock
• Programmable to 133 or 100 MHz operation
• Power management control pins for clock stop and
• Available in 56-pin SSOP
Block Diagram
spectrum technology
puts compliant to CK98 specifications
CPU clock
shut down
CPU_STOP#
SEL133/100#
PCI_STOP#
PWRDWN#
SPREAD#
X1
X2
SEL0
SEL1
Spread Spectrum Timing Solution for Serverworks Chipset
PLL2
Power
Down
XTAL
PLL 1
Logic
OSC
Tristate
Logic
÷2
÷2/÷1.5
÷2
STOP
Clock
Logic
STOP
Clock
STOP
Clock
Logic
Logic
3901 North First Street
1
2
6
1
3
5
2
REF0:1
CPU0:5
3V66_0:1
PCI_F
PCI1:5
IOAPIC0:2
48MHz
Key Specifications
Supply Voltages:...................................... V
CPU Output Jitter: ....................................................<150 ps
CPU Output Skew: ....................................................<175 ps
CPU to 3V66 Output Offset:
CPU to IOAPIC Output Offset
CPU to PCI Output Offset................. 0 to 4.0 ns (CPU leads)
Table 1. Pin Selectable Frequency.
................................................................ V
SEL133/100#
SEL133/100#
Pin Configuration
GND_3V66
GND_3V66
GND_3V66
VDD_3V66
VDD_3V66
VDD_3V66
GND_REF
VDD_REF
GND_PCI
GND_PCI
GND_PCI
GND_PCI
VDD_PCI
VDD_PCI
VDD_PCI
1
0
3V66_0
3V66_1
PCI_F
REF0
REF1
San Jose
PCI1
PCI2
PCI3
PCI4
PCI5
X1
X2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CPU0:5 (MHz)
CA 95134
133
100
0.0 to1.5 ns (CPU leads)
1.5 to 4.0 ns (CPU leads)
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Revised June 25, 2004
DD33
DD25
VDD_IOAPIC
IOAPIC2
IOAPIC1
IOAPIC0
GND_IOAPIC
VDD_CPU
CPU5
CPU4
GND_CPU
VDD_CPU
CPU3
CPU2
GND_CPU
VDD_CPU
CPU1
CPU0
GND_CPU
VDDA
GNDA
PCI_STOP#
CPU_STOP#
PWR_DWN#
SPREAD#
SEL1
SEL0
VDD_48MHZ
48MHZ
GND_48MHZ
CY28158
408-943-2600
= 3.3V ± 5%
= 2.5V ± 5%
33.3
33.3
PCI
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CY28158 Summary of contents

Page 1

... PCI5 Logic GND_PCI GND_3V66 3 GND_3V66 IOAPIC0:2 VDD_3V66 VDD_3V66 GND_3V66 3V66_0 3V66_1 VDD_3V66 SEL133/100# 1 48MHz • 3901 North First Street • San Jose CY28158 = 3.3V ± 5% DD33 = 2.5V ± 5% DD25 0.0 to1.5 ns (CPU leads) 1.5 to 4.0 ns (CPU leads) CPU0:5 (MHz) PCI 133 33.3 100 33.3 56 VDD_IOAPIC IOAPIC2 54 ...

Page 2

... PCI voltage supply 3.3V 66-MHz (AGP) voltage supply 3.3V 48-MHz (USB) voltage supply 2.5V APIC voltage supply 2.5V CPU voltage supply Analog voltage supply to PLL and Core = 18 pF. For crystals with different C , please refer to the application note, “Crystal Oscillator LOAD LOAD CY28158 Page [+] Feedback ...

Page 3

... CPU 3V66 PCI LOW LOW LOW LOW LOW LOW LOW LOW LOW Minimum Ω Buffer Type Type 1 13.5 Type 3 20 Type 5 12 CY28158 48MHZ REF IOAPIC (MHz) (MHz) (MHz) Hi-Z Hi-Z [3] [3] [3] 14.318 16.705 14.318 16.67 [3] 14.318 16.67 TCLK TCLK/16 N/A N/A 14.318 16.67 [3] 14.318 16.67 PPM – ...

Page 4

... < V < IOAPIC 48 MHZ, REF 3V66, PCI CPU IOAPIC 48 MHZ, REF 3V66, PCI Three-state 3.465V 2.625V, F DDA DD33 DD25 CY28158 Min. Max. Unit 3.135 3.465 V 2.375 2.625 V 2.375 2.625 V ° 14.318 14.318 MHz Min. Max. Unit /2 2 ...

Page 5

... CPU leads. Measured at 1.25V for 2.5V clocks and 1.5V for 3.3V clocks 3V66 leads. Measured at 1.5V CPU leads. Measured at 1.25V With all outputs running CPU and PCI clock stabilization from power-up = 2.5V, duty cycle is measured at 1.25V. DD CY28158 Min. Max. Unit = 133 MHz 160 mA CPU µA 100 µA 200 Min ...

Page 6

... Switching Waveforms Duty Cycle Timing All Outputs Rise/Fall Time OUTPUT t 2 CPU-CPU Clock Skew CPUCLK CPUCLK t 6 IOAPIC-IOAPIC Clock Skew IOAPIC IOAPIC t 8 3V66 - 3V66 Clock Skew 3V66 3V66 t 9 Document #: 38-07039 Rev CY28158 Page [+] Feedback ...

Page 7

... CPU-IOAPIC Clock Skew CPU t 13 IOAPIC [7, 8] CPU_STOP# Timing CPU (Internal) PCI (Internal) PCI_F (Free-Running) CPU_STOP# CPU, 3V66 (External) Notes: 7. CPU on and CPU off latency CPU cycles. 8. CPU_STOP# may be applied asynchronously synchronized internally. Document #: 38-07039 Rev. *B CY28158 Page [+] Feedback ...

Page 8

... Ordering Code CY28158PVC CY28158PVCT Lead Free CY28158OXC CY28158OXCT Document #: 38-07039 Rev 13, 19, 20, 21, 24, 29, 40, 44, 48 10, 16, 17, 22, 23, 27, 31, 39 CY28158 43, 47, 51, 56 Package Name Package Type O56 56-Pin SSOP O56 56-Pin SSOP- Tape and Reel O56 56-Pin SSOP ...

Page 9

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY28158 51-85062-C ...

Page 10

... Document Title: CY28158 Spread Spectrum Timing Solution for Serverworks Chipset Document Number: 38-07039 Issue Orig. of REV. ECN NO. Date Change ** 107005 08/08/01 IKA *A 122732 12/16/02 RBI *B 237871 See ECN RGL Document #: 38-07039 Rev. *B Description of Change New Data Sheet Added power-up requirements to operating conditions information. ...

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