CY26049-36 Cypress Semiconductor, CY26049-36 Datasheet

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CY26049-36

Manufacturer Part Number
CY26049-36
Description
Global Communications Clock Generator
Manufacturer
Cypress Semiconductor
Datasheet
www.DataSheet4U.com
Cypress Semiconductor Corporation
Document #: 38-07415 Rev. *C
Features
Benefits
• Fully integrated phase-locked loop (PLL)
• FailSafe output
• PLL driven by a crystal oscillator that is phase aligned
• Output frequencies selectable and/or programmed to
• Low-jitter, high-accuracy outputs
• Commercial and Industrial operation
• 3.3V ± 5% operation
• 16-lead TSSOP
• Integrated high-performance PLL tailored for telecom-
Logic Block Diagram
Pin Configuration
with external reference
standard communication frequencies
munications frequency synthesis eliminates the need
for external loop filter components
frequency select
Input reference
(typical 8 kHz)
FailSafe™ PacketClock™ Global Communications
FS[3:0]
ICLK
CLK/2 7
FAILSAFE
High=ICLK detected
SAFE
ICLK 1
CONTROL
VDD 5
VSS 6
FS1 3
FS2 4
XIN 8
8K 2
3901 North First Street
16-pin TSSOP
TM
CY26049-36
Top View
external pullable crystal
XIN
CONTROLLED
OSCILLATOR
(18.432 MHz)
CRYSTAL
DIGITAL
• When reference is in range, SAFE pin is driven high.
• When reference is off, DCXO maintains clock outputs.
• DCXO maintains continuous operation should the input
• Glitch-free transition simplifies system design
• Selectable output clock rates include T1/DS1, E1,
• Works with commonly available, low-cost 18.432-MHz
• Zero-ppm error for all output frequencies
• Performance guaranteed for applications that require
• Compatible across industry standard design platforms
• Industry standard package with 6.4 x 5.0 mm
16 NC
15 CLK
14 FS0
13 FS3
12 VDD
11 VSS
10 SAFE
9 XOUT
XOUT
SAFE pin is low.
reference clock fail
T3/DS3, E3, and OC-3.
crystal
an extended temperature range
and a height profile of just 1.1 mm.
LOCKED
PHASE
LOOP
San Jose
DIVIDERS
OUTPUT
,
CA 95134
Clock Generator
CLK
CLK/2
Revised July 16, 2004
8K
CY26049-36
408-943-2600
2
footprint

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CY26049-36 Summary of contents

Page 1

... FS1 3 14 FS0 FS2 4 13 FS3 VDD 5 12 VDD VSS 6 11 VSS CLK SAFE XIN 8 9 XOUT • 3901 North First Street • San Jose CY26049-36 Clock Generator 2 footprint CLK OUTPUT DIVIDERS CLK 95134 • 408-943-2600 Revised July 16, 2004 ...

Page 2

... DCXO with the reference as long as the reference is within the pull range of the crystal. In the event of a reference clock failure the DCXO maintains the last frequency and phase information of the reference clock. The unique feature of the CY26049-36 is that the DCXO www.DataSheet4U.com Document #: 38-07415 Rev. *C Pin Description Input Frequency Range is in fact the primary clocking source ...

Page 3

... Frequency Select Tables Table 1. CY26049-36 Frequency Select–Output Decoding Table–External Mode (MHz except as noted) ICLK FS3 8 kHz 0 8 kHz 0 8 kHz 0 8 kHz 0 8 kHz 0 8 kHz 0 8 kHz 0 8 kHz 0 8 kHz 1 8 kHz 1 8 kHz 1 8 kHz 1 8 kHz ...

Page 4

... DD Min. Typ 0.7 – – – – 5 – 5 – – – ± 5 – – – – CY26049-36 Max. Units – MHz – pF Ω – 25 – – – – ppm – –200 ppm – – 250 21.6 fF Max. ...

Page 5

... See Figure 2. DD LOAD Output Clock Edge Rate, Measured from 20 See Figure 2. DD LOAD t1 t2 CLK 50% 50% Figure 1. Duty Cycle Definition t2/t1 t3 80% CLK 20% CY26049-36 Min. Typ 0.7 – – – – 5 – 5 – – – ± 5 – ...

Page 6

... MAX. GAUGE PLANE 0.076[0.003] 0.05[0.002] SEATING 0.15[0.006] PLANE CY26049-36 CLK C LOAD VDD 0.1uF Operating Temperature Range Commercial 0 to 70°C Commercial 0 to 70°C Industrial –40 to 85°C Industrial –40 to 85°C Commercial 0 to 70°C Commercial 0 to 70°C Industrial – ...

Page 7

... Document History Page Document Title: CY26049-36 FailSafe™ PacketClock™ Global Communications Clock Generator Document Number: 38-07415 REV. ECN NO. Issue Date ** 114749 08/08/02 *A 120067 01/06/03 *B 128000 07/15/03 *C 244412 See ECN www.DataSheet4U.com Document #: 38-07415 Rev. *C Orig. of Change CKN New Data Sheet CKN Changed “FailSafe is a trademark of Silicon Graphics, Inc.” to read “FailSafe is a trademark of Cypress Semiconductor” ...

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