AN1827 Freescale Semiconductor / Motorola, AN1827 Datasheet - Page 7
![no-image](/images/no-image-200.jpg)
AN1827
Manufacturer Part Number
AN1827
Description
Programming and Erasing FLASH Memory on the MC68HC908AS60
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
1.AN1827.pdf
(60 pages)
- Current page: 7 of 60
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AN1827
MOTOROLA
FDIV1 — Frequency Divide Control Bit
FDIV0 — Frequency Divide Control Bit
BLK1 — Block Erase Control Bit
BLK0 — Block Erase Control Bit
HVEN — High-Voltage Enable Bit
MARGIN — Margin Read Control Bit
This read/write bit together with FDIV0 selects the factor by which
the charge pump clock is divided from the bus clock. See
Pump.
This read/write bit together with FDIV1 selects the factor by which
the charge pump clock is divided from the bus clock. See
Pump.
This read/write bit together with BLK0 allows erasing of blocks of
varying sizes. See
block sizes.
This read/write bit together with BLK1 allows erasing of blocks of
varying sizes. See
block sizes.
This read/write bit enables the charge pump to drive high voltages
for program and erase operations in the array. HVEN can be set
only if either PGM = 1 or ERASE = 1 and the proper sequence for
erase or page program/margin read is followed.
This read/write bit configures the memory for the margin read
operation. MARGIN cannot be set if HVEN = 1. MARGIN will
automatically clear (MARGIN = 0) if asserted when HVEN = 1.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
1 = Margin read operation selected
0 = Margin read operation unselected
Go to: www.freescale.com
Erase Operation
Erase Operation
for a description of available
for a description of available
Control and Block Protect Registers
Application Note
Charge
Charge
7
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