DS26334 Dallas Semiconductor, DS26334 Datasheet - Page 86

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DS26334

Manufacturer Part Number
DS26334
Description
E1/T1/J1 Shortand Long-Haul Line Interface Unit
Manufacturer
Dallas Semiconductor
Datasheet

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Register Name:
Register Description:
Register Address (LIUs 1–8):
Register Address (LIUs 9–16):
Bit #
Name
Default
Bit 6: QRSS Enable (QRSS). When 0, the pattern generator configuration is controlled by PTS, PLF[4:0], and
PTF[4:0], and BSP[31:0]. When 1, the pattern generator configuration is forced to a PRBS pattern with a
generating polynomial of x
output bits are all zero.
Bit 5: Pattern Type Select (PTS). When 0, the pattern is a PRBS pattern. When 1, the pattern is a repetitive
pattern.
Bits 4 to 0: Pattern Length Feedback (PLF[4:0]). These five bits control the “length” feedback of the pattern
generator. The “length” feedback will be from bit n of the pattern generator (n = PLF[4:0] +1). For a PRBS signal,
the feedback is an XOR of bit n and bit y. For a repetitive pattern the feedback is bit n.
Register Name:
Register Description:
Register Address (LIUs 1–8):
Register Address (LIUs 9–16):
Bit #
Name
Default
Bits 4 to 0: Pattern Tap Feedback (PTF[4:0]). These five bits control the PRBS “tap” feedback of the pattern
generator. The “tap” feedback will be from bit y of the pattern generator (y = PTF[4:0] +1). These bits are ignored
when programmed for a repetitive pattern. For a PRBS signal, the feedback is an XOR of bit n and bit y.
7
0
7
0
QRSS
20
+ x
6
0
6
0
17
BPCR1
BERT Pattern Configuration Register 1
02h
22h
BPCR2
BERT Pattern Configuration Register 2
03h
23h
+ 1. The output of the pattern generator will be forced to one if the next fourteen
PTS
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
5
0
5
0
86 of 121
PLF4
PTF4
4
0
4
0
PLF3
PTF3
3
0
3
0
PLF2
PTF2
0
0
2
2
PLF1
PTF1
1
0
1
0
PLF0
PTF0
0
0
0
0

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