DS26334 Dallas Semiconductor, DS26334 Datasheet
DS26334
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DS26334 Summary of contents
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... GENERAL DESCRIPTION The DS26334 is a 16-channel short/long-haul line interface unit (LIU) that supports E1/T1/J1 from a single 3.3V power supply. A single bill of material can support E1/T1/J1 that requires termination. Redundancy is nonintrusive monitoring, optimal high-impedance modes and configurable 1:1 enhancements. An on-chip synthesizer generates the E1/T1/J1 clock rates by a single master clock input of various frequencies ...
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... ESCRIPTION 6.1.1 Primary Register Bank ........................................................................................................................ 48 6.1.2 Secondary Register Bank ................................................................................................................... 63 6.1.3 Individual LIU Register Bank............................................................................................................... 66 6.1.4 BERT Registers .................................................................................................................................. 85 7 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT ...................................92 7.1 TAP C S ONTROLLER TATE 7.1.1 Test-Logic-Reset................................................................................................................................. 93 7.1.2 Run-Test-Idle ...................................................................................................................................... 93 DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit TABLE OF CONTENTS ..........................................................................................6 ...............................................................................................................48 M ..............................................................................................93 ACHINE 2 of 121 ...
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... YSTEM IMING 9.5 JTAG T ..............................................................................................................................115 IMING 10 PIN CONFIGURATION .................................................................................................................116 11 PACKAGE INFORMATION ..........................................................................................................117 11.1 256-B TE-CSBGA (17 ALL 12 THERMAL INFORMATION...........................................................................................................118 13 DATA SHEET REVISION HISTORY.............................................................................................120 DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit ................................................................................................................96 V .....................................................................................98 UTPUT OLTAGE ............................................................................................... ...............................................................100 IMING HARACTERISTICS 17 ) (56-G6028-001) .............................................................117 121 ...
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... Figure 9-10. Serial Bus Timing Read Operation with CLKE = 0.............................................................................. 112 Figure 9-11. Serial Bus Timing Read Operation with CLKE = 1.............................................................................. 112 Figure 9-12. Transmitter Systems Timing ............................................................................................................... 113 Figure 9-13. Receiver Systems Timing ................................................................................................................... 114 Figure 9-14. JTAG Timing ....................................................................................................................................... 115 Figure 10-1. 256-Ball TE-CSBGA............................................................................................................................ 116 DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit LIST OF FIGURES 4 of 121 ...
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... Table 4-1. Pin Descriptions........................................................................................................................................ 10 Table 5-1. Parallel Port Mode Selection and Pin Functions ...................................................................................... 18 Table 5-2. Telecommunications Specification Compliance for DS26334 Transmitters ............................................ 21 Table 5-3. Registers Related to Control of DS26334 Transmitters ........................................................................... 21 Table 5-4. Template Selections for Short-Haul Mode ............................................................................................... 22 Table 5-5. Template Selections for Long-Haul Mode ................................................................................................ 22 Table 5-6. LIU Front-End Values ............................................................................................................................... 26 Table 5-7. Loss Criteria ANSI T1.231, ITU-T G.775, and ETS 300 233 Specifications ............................................ 28 Table 5-8 ...
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... STANDARDS COMPLIANCE 1.1 Telecom Specifications compliance The DS26334 LIU meets all the relevant latest Telecommunications Specifications. The following provides the T1 and E1 Specifications and relevant sections that are applicable to the DS26334. • T1-Related Telecommunications Specifications • ANSI T1.102: Digital Hierarchy Electrical Interface • ...
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... Partially internal impedance matching supports either a 1 1:2 transformer on the receive line 1:2 transformer is used, the external termination resistor should be 30Ω. For long-haul applications, a 1:1 transformer on the receive line is preferred. The DS26334 drives the line from the TTIP and TRING pins by a 1:2 coupling transformer. ...
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... BLOCK DIAGRAMS Figure 3-1. Block Diagram TYPICAL OF ALL 16 CHANNELS RRING RTIP TRING TTIP OE Reset Reset DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit T1CLK E1CLK MUX VCO/PLL Unframed All Ones Insertion Control Port Interface and Interrupt 121 DS26334 LOS RPOS/RDAT Receive Logic ...
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... Detect T1.231 POS NEG Decoder (G.703, T1.102) BPVs, Code Violatiions Figure 3-3. Transmit Logic Detail To Remote Loopback BPV Insert DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit NRZ Data B8ZS/HDB3/AMI BPV/CV/EXZ (T1.231, O.161) AIS Detector G.775, ETSI 300233, T1.231 B8ZS/HDB3/AMI Coder (G.703, T1.102) ...
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... A14 RTIP15 A9 RTIP16 A4 DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit TYPE ANALOG TRANSMIT AND RECEIVE Transmit Bipolar Tip for Channels 1–16. These pins are differential line driver tip outputs. These pins can be high impedance if pin OE is low. When “1” is set in the Output Enable Register associated TTIPn pin will be enabled when the OE pin is high ...
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... RTIPn and RRINGn can provide internal impedance matching with external resistance for E1 75Ω, E1 120Ω, T1 100Ω 110Ω. DIGITAL Tx/Rx Transmit Positive Data Input for Channels 1–6. When DS26334 is configured in dual-rail mode, the data input to TPOSn is output as a positive pulse on the line (tip and ring). ...
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... RNEG15/CV15 C7 RNEG16/CV16 J3 DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit Transmit Clock for Channels 1–16. The transmit clock has to be 1.544MHz for T1 or 2.048MHz for E1 mode. TCLKn is the clock used to sample the data TPOS/TNEG or TDAT on the falling edge. The expected TCLK can be inverted. ...
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... B3 I CSB P14 I DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit FUNCTION Receive Clock for Channels 1–16. The receive data (RPOS/RNEG) is clocked out on the rising edge of RCLK given receiver is in power-down mode the RCLK is high impedance. Upon an LOS being detected, the RCLK is switched from the recovered clock to MCLK. ...
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... INTB D7 open drain DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit Shift Clock. In the serial host mode, this pin is the serial clock. Data on SDI is clocked on the rising edge of SCLK. The data is clocked on SDO on the rising edge of SCLK if CLKE is high. If CLKE is low the data on SDO is clocked on the falling edge of SCLK. ...
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... I, TDI B15 pullup DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit FUNCTION Data Bus 7–0. In nonmultiplexed host mode, these pins are the bidirectional data bus. Address/Data Bus 7–0. In multiplexed host mode, these pins are the bidirectional address/data bus. Note: AD7 and AD6 do not carry address information ...
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... J7 DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit FUNCTION RESET Reset Bar. This is the asynchronous reset input bar internally pulled high. A 1μs low on this pin will reset the DS26334 registers to default value. POWER SUPPLIES 3.3V Digital Power Supply Digital Ground 3.3V Power Supply for the Transmitter. All VDDT pins must be connected to VDDT, which has ...
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... Port Operation 5.1.1 Serial Port Operation Setting MODESEL = ‘low’ enables the serial bus interface on the DS26334. Port read/write timing is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host. See Section AC timing of the serial port. All serial port accesses are LSB first when BSWP pin is high and MSB first when BSWP is low ...
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... SDO 5.1.2 Parallel Port Operation When using the parallel interface on the DS26334 the user has the option for either multiplexed bus operation or nonmultiplexed bus operation. The ALE pin is pulled high in nonmultiplexed bus operation. The DS26334 can operate with either Intel or Motorola bus-timing configurations selected by MOTEL pin. This pin being high selects the Intel mode ...
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... Master Clock The DS26334 requires 2.048MHz ±50ppm or 1.544MHz ±50ppm or multiple thereof. The receiver uses the MCLK as a reference for clock recovery, jitter attenuation and generating RCLK during LOS. The AIS transmission uses MCLK for transmit all ones condition. See register the master clock adapter will generate both 2 ...
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... The line driver supports internal impedance matching for 75Ω, 100Ω, 110Ω, and 120Ω modes. The DS26334 drivers have short and open circuit driver fail monitor detection. There pin that can high impedance the transmitter outputs for protection switching when low. The individual transmitters are by default in high impedance ...
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... AMI Coding, B8ZS Substitution, DS1 Electrical Interface T1 Telecom Pulse Mask compliance T1 Telecom Pulse Mask compliance Transmit Electrical Characteristics for E1 Transmission and Return Loss Compliance Table 5-3. Registers Related to Control of DS26334 Transmitters REGISTER Transmit All Ones Enable Driver Fault Monitor Status Driver Fault Monitor Interrupt Enable ...
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... Transmit Line Templates The DS26334 transmitters can be selected individually to meet the pulse masks for E1 and T1/J1 mode. The T1/J1 pulse mask is shown in the Transmit Pulse Template and can be configured on an individual LIU basis. The transmit template is selected via the TS[2:0] bits in the the TIMPOFF and the TIMPRM bits of the same register. When transmit impedance matching is enabled TIMPRM will select between 75Ω ...
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... DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit - ...
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... Figure 5-7. E1 Transmit Pulse Templates 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 -200 DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 194ns 219ns -150 -100 - TIME (ns 121 269ns G.703 Template 100 150 200 250 ...
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... It is recommended that the LIU for the transmitter be configured as described in Figure 5-8. LIU Front-End 3.3V VDDTn C1 C2 GNDTn TRING (One Channel) 3.3V RTIP AVDDn C3 C4 A75 AVSSn RRING 3.3V TVS1 DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit Dt TTIP optional A100 A110 termination 121 Figure 5-8 ...
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... B8ZS substitution is defined in ANSI T1.102 and HDB3 in ITU-T G.703 standards. 5.4.6 Transmit Power-Down The transmitter will be powered down if the relevant bits in the impedance when TPDE is set. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 75Ω COAX, 120Ω TWISTED PAIR, 100/110Ω TWISTED PAIR Ct 560pF typical ...
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... Receiver The DS26334’s 16 receivers are all identical. A 1:2 or 1:1 transformer can be used on the receive side (selected by the RTR bit), but only a 1:1 transformer can be used if fully internal impedance match is enabled. Fully internal receive impedance match does not require the use of any external resistor on the receive line. If partially internal impedance matching is selected, the DS26334 will need only an external 120Ω ...
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... Loss of Signal The DS26334 uses both the digital and analog loss-detection method in compliance with the latest ANSI T1.231 for T1/J1 and ITU-T G.775 or ETS 300 233 for E1 mode of operation. LOS is detected if the receiver level falls bellow a threshold analog voltage for certain duration. Alternatively, this can be termed as having received “ ...
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... Criteria received. AIS 3 or more zeros in each of 2 Clearance consecutive 512-bit streams Criteria received. Table 5-9. AIS Detection and Reset Criteria for DS26334 CRITERIA ITU-T G.775 for E1 AIS 2 or fewer zeros in each of 2 Detection consecutive 512-bit streams Criteria received. ...
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... The Single-Rail Mode Select Register (SRMS) is used for selection of dual-rail or single-rail mode. 5.5.10 Bipolar Violation and Excessive Zero Detector The DS26334 detects HDB3 code violations, BPVs, and excessive zero errors. The reporting of the errors is done through the RNEGn/CVn pin in single-rail mode and the violations are only detected in E1 mode with HDB3 encoding ...
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... Jitter Attenuator The DS26334 contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits via the JADS bit in register GC. It can also be controlled on an individual LIU basis by settings in the The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications ...
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... TTIP1 and TRING1. While monitoring, Channel 9 can be configured in remote loopback and the monitored signal can be output on TTIP9 and TRING9. 5.8 Loopbacks The DS26334 provides four loopbacks for diagnostic purposes: analog loopback, digital loopback, remote loopback, and dual loopback. Dual loopback is accomplished by turning on digital loopback and remote loopback at the same time. ...
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... RCLK RPOS RNEG DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit ...
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... BERT There are two bit error-rate testers available on the DS26334. One BERT can be mapped into LIUs 1–8 and the other into LIUs 9–16 via the BTCR Each BERT transmitter, by default, replaces data from TPOS and TNEG; each BERT receiver, by default, samples recovered data from RTIP and RRING ...
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... Receive BERT Bit Error Count Register (RBECR) will be updated upon the reception of a Performance Monitor Update signal (e.g., BCR.LPMU). This signal will update the registers with the values of the counters since the last update and will reset the counters. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit BPCR REGISTER ...
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... Automatic pattern re-synchronization can be disabled. See Figure 5-13 for the PRBS synchronization diagram. Figure 5-13. PRBS Synchronization State Diagram Sync 1 bit error Verify 32 bits loaded DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit Load 36 of 121 ...
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... If they match, only the bit count is incremented. The bit count and bit error count are not incremented when an OOS condition exists. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit Match ...
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... The method of single error insertion is programmable (register or input). If pattern inversion is enabled, the data stream is inverted before the overhead/stuff bits are inserted. Pattern inversion is programmable (on or off). DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 38 of 121 n ...
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... Primary bank of registers. Note that bank selection for the lower set of registers (LIUs 1–8) is controlled only by the ADDP at 1F hex and that bank selection for the upper set of registers (LIUs 9–16) is controlled only by the ADDP at 3F hex. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit ADDP 39 of 121 ...
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... Template Select Transmitter Template Select Output Enable Configuration Alarm Indication Signal Status AIS Interrupt Enable AIS Interrupt Status Reserved Address Pointer for Bank Selection DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit ADDRESS FOR CH 1–8 HEX FOR PARALLEL SERIAL NAME CH 1–8 INTERFACE ...
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... Line Code Selection Not Used Receive Power-Down Enable Transmit Power-Down Enable Excessive Zero Detect Enable Code Violation Detect Enable Bar Not Used Address Pointer for Bank Selection DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit ADDRESS FOR CHANNELS 1–8 HEX PARALLEL SERIAL NAME FOR INTERFACE INTERFACE CH 1– ...
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... Transmit Clock Invert TCLKI Clock Control Register CCR RCLK Disable Upon LOS RDULR Global Interrupt Status Control GISC Address Pointer for Bank Selection ADDP DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit ADDRESS FOR CHANNELS 1–8 HEX PARALLEL SERIAL FOR INTERFACE INTERFACE CH 1–8 A[7:0] (HEX) ...
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... RBCR1 Receive Bit Count Register 2 RBCR2 Receive Bit Count Register 3 RBCR3 Receive Bit Count Register 4 RBCR4 Reserved Address Pointer for Bank Selection DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit ADDRESS FOR CHANNELS 1–8 HEX FOR PARALLEL NAME CH 1–8 INTERFACE INTERFACE A[7:0] (HEX) ...
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... AISIE 34 RW AISIE16 AISIS 35 R AISIS16 Not Used 36-3E — — ADDP 3F RW ADDP7 Note: Underlined bits are read only. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit BIT 6 BIT 5 BIT 4 BIT 3 ID6 ID5 ID4 ALBC7 ALBC6 ALBC5 ALBC4 RLBC7 RLBC6 RLBC5 RLBC4 TAOE7 ...
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... TPDE 24 RW TPDE16 EZDE 25 RW EZDE16 CVDEB 26 RW CVDEB16 Not Used 27–3E — ADDP 3F RW ADDP7 DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit BIT 7 BIT 6 BIT 5 BIT 4 SRMS7 SRMS6 SRMS5 LCS8 LCS7 LCS6 LCS5 — — — — RPDE7 RPDE6 RPDE5 TDPE7 ...
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... Not Used 35 RW — RDULR 36 RW RDULR16 Not Used 3E RW — ADDP 3F RW ADDP7 Note: Underlined bits are read only. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit BIT 6 BIT 5 BIT 4 IJAE7 IJAE6 IJAE5 IJAPS7 IJAPS6 IJAPS5 IJAPS4 IJAFDS7 IJAFDS6 IJAFDS5 IJAFDS4 IJAFLT7 IJAFLT6 ...
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... R RBCR3 RBCR4 Not Used 1C–1E 3C–3E — ADDP Note: Underlined bits are read only. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit BIT 7 BIT 6 BIT 5 BIT 4 PMUM LPMU RNPL RPIC — — — — — QRSS PTS PLF4 — — ...
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... Bits Analog Loopback Control Bits Channel n (ALBCn). When this bit is set, LIUn is placed in analog loopback. TTIP and TRING are looped back to RTIP and RRING. The data at RTIP and RRING is ignored. The LOS detector is still in operation. The jitter attenuator is in use if enabled for the transmitter or receiver. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 5 4 ...
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... Name LOSS16 LOSS15 Default 0 0 Bits Loss of Signal Status Channel n (LOSSn). When this bit is set, an LOS condition has been detected on LIUn. The criteria and conditions of LOS are described in Section 5.5.6. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit RLBC6 RLBC5 RLBC4 ...
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... Register Address (LIUs 9–16): 27h Bit # 7 6 Name DFMIE16 DFMIE15 Default 0 0 Bits Driver Fault Monitor Interrupt Enable Channel n (DFMIEn). When this bit is set, a change in DFM status can generate an interrupt. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit DFMS6 DFMS5 DFMS4 ...
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... Bits Driver Fault Status Register Channel n (DFMISn). When this bit is set, it indicates a DFM status has transitioned from “0 to 1” or “1 to 0” and was detected for LIUn. The bit for LIUn is enabled by register DFMIE (07h). This bit when latched is cleared on a read operation. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 5 4 ...
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... Bits Software Reset (SWRU). Whenever any write is performed to this register, at least 1μs reset will be generated that resets the upper set of registers (LIUs 9–16). All the registers will be restored to their default values. A read operation will always read back all zeros. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 5 4 ...
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... Bits G.772 Monitoring Control (GMC). These bits are used to select transmitter or receiver for nonintrusive monitoring. Receiver 9 is used to monitor Channels one receiver from RTIP10– RTIP16/RRING10–RRING16 or of one transmitter from TTIP10–TTIP16/TRING10–TRING16. See DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 5 4 ...
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... DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit GMC0 SELECTION 0 No Monitoring 1 Receiver 2 0 Receiver 3 1 Receiver 4 0 Receiver 5 1 Receiver 6 0 Receiver 7 1 Receiver Monitoring 1 Transmitter 2 0 Transmitter 3 1 ...
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... Default 0 0 Bits Automatic Transmit All Ones Select Channel n (ATAOSn). When this bit is set all ones signal is sent if an LOS is detected for LIUn. “All Ones Signal” uses MCLK as the reference clock. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit DLBC6 ...
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... Note that when bit JAE is set, the settings in the Bit 0: Jitter Attenuator Enable (JAE). When this bit is set the jitter attenuator is enabled. The settings in the register will be ignored if this register is set. If reset, the IJAE register will have control. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 5 4 ...
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... Note that when bit JAE is set, the settings in Bit 0: Jitter Attenuator Enable (JAE). When this bit is set the jitter attenuator is enabled. The settings in the register will be ignored if this register is set. If reset, the IJAE register will have control. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 5 4 ...
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... RTIP and RRING is high impedance). When this bit is reset, the RIMPON register bit will control receive impedance match. Bits TST Template Select Transceiver [2:0] (TST[2:0]). TST[2:0] is used to select the transceiver that the Transmit Template Select Register (0x11) will configure for LIUs 9–16. See DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit RHPMC — ...
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... Table 6-11. TST Template Select Transmitter Register (LIUs 1–8) TST[2:0] CHANNEL 000 1 001 2 010 3 011 4 Table 6-12. TST Template Select Transmitter Register (LIUs 9–16) TST[2:0] CHANNEL 000 9 001 10 010 11 011 12 DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit TST[2:0] CHANNEL 100 5 101 6 110 7 111 8 TST[2:0] CHANNEL 100 13 101 14 110 15 111 121 ...
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... ABAM 000 G.703 coaxial and twisted pair cable 001 and 010 Reserved 011 0db CSU 100 -7.5dB CSU 101 -15dB CSU 110 -22.5dB CSU DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit TIMPRM — — Table 6-13 for bit selection of TS[2:0]. TEMPLATE SELECTION ...
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... Bits Alarm Indication Signal Channel n (AISn). This bit will be set when AIS is detected for LIUn. The criteria for AIS selection is detailed in Section 5.5.7. The selection of the AIS criteria is done by settings in the LASCS (0D) register. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit OE6 ...
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... Bits AIS Interrupt Status Channel n (AISISn). This bit is set when AIS ransitions from a “0 to 1” or “1 to 0” and interrupts are enabled by the AISIE(14) register for LIUn. If set, this bit is cleared on a read operation or when the interrupt enable register is disabled. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 5 4 ...
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... Name SRMS16 SRMS15 Default 0 0 Bits Single-Rail Mode Select Channel n (SRMSn). When this bit is set single-rail mode is selected for the system transmit and receive n. If this bit is reset, dual-rail is selected. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit ADDP5 ADDP4 ADDP3 0 ...
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... Register Address (LIUs 9–16): 24h Bit # 7 6 Name TPDE16 TPDE15 Default 0 0 Bits Transmit Power-Down Enable Channel n (TPDEn). When this bit is set the transmitter for LIUn is powered down. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit LCS6 LCS5 LCS4 ...
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... Bits Code Violation Detect Enable Bar Channel n (CVDEBn). If this bit is set, code violation detection is disabled for the LIUn. If this bit is reset, code violation detection is enabled. Code violation detection is only relevant when HDB3 decoding is enabled DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 5 4 ...
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... Bits Individual Jitter Attenuator Position Select Channel n (IJAPSn). When this bit is set high, the jitter attenuator is in the receive path n; when this bit is default or set low the jitter attenuator is in the transmit path n. Note that if the GC.JAE register bit is set, this register will be ignored. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 5 4 ...
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... Name ISCPD16 ISCPD15 Default 0 0 Bits Individual Short-Circuit Protection Disable n. (ISCPDn). When this bit is set the short-circuit protection is disabled for the individual transmitter n. Note that if the register will be ignored. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit IJAFDS6 IJAFDS5 IJAFDS4 ...
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... Bits Individual AIS Enable During Loss n (IAISELn). When this bit is set, individual AIS enable during loss is enabled for the individual receiver n, and AIS is sent to the system side upon detection of an LOS. Note that if the GC.AISEL register bit is set, the settings in this register will be ignored. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 5 4 ...
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... Channels 9 to 16. Bit 1: Frequency Select (FREQS). In conjunction with MPS[1:0] selects the external MCLK frequency for the DS26334. If this bit is set the external Master clock can be 1.544MHz or multiple thereof. If not set the external master clock can be 2.048MHz or multiple thereof. See controller functionality of Channels 9 to 16. ...
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... Register Address (LIUs 9–16): 27h Bit # 7 6 Name SHLHS16 SHLHS15 Default 0 0 Bits Short-Haul/Long-Haul Select n. (SHLHSn). When this bit is set, the long-haul mode is enabled for the individual transmitter n. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit SHLHS6 SHLHS5 SHLHS4 ...
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... Note that in order to use the fully internal receive impedance termination, a 1:1 transformer must be used and this bit must be set to 1. Bits Channel 9 Receive Sensitivity/Monitor Select [2:0] (C9RSM[2:0]). Bits C9RSM[2:0] are used to select the receiver sensitivity level and the monitor mode resistive gain. See DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit ...
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... Note that in order to use the fully internal receive impedance termination, a 1:1 transformer must be used and this bit must be set to 1. Bits Channel 11 Receive Sensitivity/Monitor Select [2:0] (C11RSM[2:0]). Bits C11RSM[2:0] are used to select the receiver sensitivity level and the monitor mode resistive gain. See DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit ...
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... Note that in order to use the fully internal receive impedance termination, a 1:1 transformer must be used and this bit must be set to 1. Bits Channel 13 Receive Sensitivity/Monitor Select [2:0] (C13RSM[2:0]). Bits C13RSM[2:0] are used to select the receiver sensitivity level and the monitor mode resistive gain. See DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit ...
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... Note that in order to use the fully internal receive impedance termination, a 1:1 transformer must be used and this bit must be set to 1. Bits Channel 15 Receive Sensitivity/Monitor Select [2:0] (C15RSM[2:0]). Bits C15RSM[2:0] are used to select the receiver sensitivity level and the monitor mode resistive gain. See DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit ...
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... Bits Channel 10 Receive Signal Level [3:0] (C10RSL[3:0]). C10RSL[3:0] bits provide the receive signal level as shown in Table 6-17. Bits Channel 9 Receive Signal Level [3:0] (C9RSL[3:0]). C9RSL[3:0] bits provide the receive signal level as shown in Table 6-17. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit RECEIVER RECEIVER SENSITIVITY MONITOR (MAXIMUM MODE GAIN LOSS) ...
Page 76
... Bits Channel 12 Receive Signal Level [3:0] (C12RSL[3:0]). C12RSL[3:0] bits provide the receive signal level as shown in Table 6-17. Bits Channel 11 Receive Signal Level [3:0] (C11RSL[3:0]). C11RSL[3:0] bits provide the receive signal level as shown in Table 6-17. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit E1 >-2.5 -2 -7.5 -7.5 to -10 -10 to -12.5 -12.5 to -15 -15 to -17 ...
Page 77
... Bits Channel 14 Receive Signal Level [3:0] (C14RSL[3:0]). C14RSL[3:0] bits provide the receive signal level as shown in Table 6-17. Bits Channel 13 Receive Signal Level [3:0] (C13RSL[3:0]). C13RSL[3:0] bits provide the receive signal level as shown in Table 6-17. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit C6RSL1 C6RSL0 C5RSL3 0 ...
Page 78
... Bits Channel 16 Receive Signal Level [3:0] (C16RSL[3:0]). C16RSL[3:0] bits provide the receive signal level as shown in Table 6-17. Bits Channel 15 Receive Signal Level [3:0] (C15RSL[3:0]). C15RSL[3:0] bits provide the receive signal level as shown in Table 6-17. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit C8RSL0/ C8RSL1 C7RSL3 CALSTAT ...
Page 79
... The BERT register set should be written and read to only after being enabled. The BERT is only active for one LIU at a time selected by BTS[2:0]. If the BERT is enabled on the transmit (line) side, the BERT data will be automatically B8ZS/HDB3 encoded before it is transmitted. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 5 4 ...
Page 80
... Bits BPV Error Insertion Register n (BEIRn). A 0-to-1 transition on this bit will cause a single bipolar violation (BPV inserted into the transmit data stream Channel n. This bit must be cleared and set again for a subsequent error to be inserted. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit CHANNEL BERT BTS1 ...
Page 81
... Bit Receive Clock Invert n (RCLKIn). When this bit is set the RCLK for Channel n is inverted. This aligns RPOS/RNEG on the falling edge of RCLK. When reset or default RPOS/RNEG is aligned on the rising edge of RCLK. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit LVDS6 ...
Page 82
... Bits Transmit Clock Invert n (TCLKIn). When this bit is set the expected TCLK for Channel n is inverted. TPOS/TNEG should be aligned on the falling edge of TCLK. When reset or default TPOS/TNEG should be aligned on the rising edge of TCLK. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit ...
Page 83
... DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit PCLKS0 TECLKS CLKA3 Table 6-20 PLL CLOCK SELECTED MC.PCLKI[1:0]=10 RCLK9 RCLK10 RCLK11 RCLK12 RCLK13 RCLK14 ...
Page 84
... Bit 0: Clear On Write Enable (CWE). When this bit is set the clear on write is enabled for all the latched interrupt status registers. The host processor must write the latched interrupt status register bit position before the particular bit will be cleared. Default for all the latched interrupt status registers is to clear on a read. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 5 4 ...
Page 85
... BSP[31:0] must not change from the time this bit transitions from until four TXCK clock cycles after this bit transitions from Bit 0: Transmit Pattern Inversion Control (TPIC). When 0, the transmit outgoing data stream is not altered. When 1, the transmit outgoing data stream is inverted. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit ...
Page 86
... Bits Pattern Tap Feedback (PTF[4:0]). These five bits control the PRBS “tap” feedback of the pattern generator. The “tap” feedback will be from bit y of the pattern generator (y = PTF[4:0] +1). These bits are ignored when programmed for a repetitive pattern. For a PRBS signal, the feedback is an XOR of bit n and bit y. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 5 4 ...
Page 87
... BSP(31) will be the first bit output on the transmit side for a 32-bit repetitive pattern or 32-bit length PRBS. BSP(31) will be the first bit input on the receive side for a 32-bit repetitive pattern. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 5 4 ...
Page 88
... Bit 1: Bit Error Count (BEC). When 0, the bit error count is zero. When 1, the bit error count is one or more. Bit 0: Out Of Synchronization (OOS). When 0, the receive pattern generator is synchronized to the incoming pattern. When 1, the receive pattern generator is not synchronized to the incoming pattern. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 5 4 ...
Page 89
... Bit 1: Bit Error Count Interrupt Enable (BECIE). This bit enables an interrupt if the BECL bit is set interrupt disabled 1 = interrupt enabled Bit 0: Out Of Synchronization Interrupt Enable (OOSIE). This bit enables an interrupt if the OOSL bit is set interrupt disabled 1 = interrupt enabled DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit — — ...
Page 90
... Bits BERT Bit Error Count (BEC[23:0]). These 24 bits indicate the number of bit errors detected in the incoming data stream. This count stops incrementing when it reaches a count of FF FFFFh. The associated bit error counter will not incremented when an OOS condition exists. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 5 4 ...
Page 91
... Bits BERT Bit Count (BC[31:0]). These 32 bits indicate the number of bits in the incoming data stream. This count stops incrementing when it reaches a count of FFFF FFFFh. The associated bit counter will not incremented when an OOS condition exists. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 5 4 ...
Page 92
... JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT The DS26334 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26334 contains the following as required by IEEE 1149.1 Standard Test-Access Port and Boundary-Scan Architecture: ...
Page 93
... A falling edge on TCLK while in the Update-DR state will latch the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output due to changes in the shift register. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 93 of 121 ...
Page 94
... TCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on TCLK with TMS LOW will put the controller in the Run-Test-Idle state. With TMS HIGH, the controller will enter the Select-DR-Scan state. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 94 of 121 ...
Page 95
... Figure 7-2. TAP Controller State Diagram Test Logic 1 Reset 0 Run Test/ 0 Idle DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 1 1 Select DR-Scan Capture DR Capture IR 0 Shift Exit DR 0 Pause Exit2 DR 1 Update DR Update 121 1 Select ...
Page 96
... TDO. A rising edge on TCLK in the Exit1-IR state or the Exit2-IR state with TMS HIGH will move the controller to the Update-IR state. The falling edge of that same TCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions supported by the DS26334 and its respective operational binary codes are shown in Table 7-1 ...
Page 97
... IEEE 1149.1 requires a minimum of two test registers: the Bypass Register and the Boundary Scan Register. An optional test register has been included with the DS26334 design. This test register is the Identification Register and is used with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller. ...
Page 98
... Note 3: Power dissipation with all ports active, TTIP and TRING driving a 25Ω load, for an all-ones data density. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit (except V )…………………………………………….-0.3V to +5.5V ...
Page 99
... T1 and T1.231 Specification Compliance; 192 zeros for E1 and G.775 Specification Compliance; 2048 zeros for ETS 300 233 compliance. Note 3: 24 ones in 192-bit period for T1.231; 192 ones for G.775; 192 ones for ETS 300 233. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit SYMBOL MIN TYP 2 ...
Page 100
... RDYB t15 Active output delay time from RDB Note 1: The timing parameters in this table are guaranteed by design (GBD). Note 2: The input/output timing reference level for all signals is V DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit Figure 9-1 and Figure DESCRIPTION /2. DD 100 of 121 9-2 ...
Page 101
... Figure 9-1. Intel Nonmuxed Read Cycle CSB RDB ALE=(1) t13 A[5:0] D[7:0] RDYB DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit t2 t1 ADDRESS t6 DATA OUT t8 t15 101 of 121 t14 ...
Page 102
... Figure 9-2. Intel Mux Read Cycle CSB RDB t11 ALE t4 AD[7:0] ADDRESS RDYB DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit t2 t1 t12 t6 t10 DATA OUT t8 t15 102 of 121 t14 ...
Page 103
... Hold time from ALE inactive A[5:0] t14 Valid address to WRB inactive Note 1: The timing parameters in this table are guaranteed by design (GBD). Note 2: The input/output timing reference level for all signals is V DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit Figure 9-3 and Figure DESCRIPTION /2. DD 103 of 121 9-4 ...
Page 104
... Figure 9-3. Intel Nonmux Write Cycle CSB WRB ALE=(1) A[5:0] D[7:0] RDYB DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit t2 t1 t14 ADDRESS t6 WRITE DATA t8 t9 104 of 121 t5 t10 ...
Page 105
... Figure 9-4. Intel Mux Write Cycle CSB WRB t12 ALE t4 AD[7:0] ADDRESS RDYB DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit t2 t1 t13 t8 t9 105 of 121 WRITE DATA t11 t10 ...
Page 106
... Hold time from DSB inactive A[5:0] t16 Setup time to DSB active Note 1: The timing parameters in this table are guaranteed by design (GBD). Note 2: The input/output timing reference level for all signals is V DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit Figure 9-5 and Figure DESCRIPTION /2. DD 106 of 121 9-6 ...
Page 107
... Figure 9-5. Motorola Nonmux Read Cycle CSB RWB DSB ASB=(1) t16 A[5:0] D[7:0] ACKB DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit ADDRESS t8 t13 t14 107 of 121 t3 t5 t15 t10 DATA OUT t11 t12 ...
Page 108
... Figure 9-6. Motorola Mux Read Cycle CSB t4 RWB DSB ASB t6 AD[7:0] ADDRESS ACKB DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit t2 t1 t14 t7 t8 DATA OUT t13 t14 108 of 121 t3 t5 t10 t11 t12 ...
Page 109
... Output delay time from DSB active A[5:0] t15 Hold time from DSB Note 1: The timing parameters in this table are guaranteed by design (GBD). Note 2: The input/output timing reference level for all signals is V DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit Figure 9-7 and Figure DESCRIPTION /2. DD 109 of 121 9-8 ...
Page 110
... Figure 9-7. Motorola Nonmux Write Cycle CSB t4 RWB DSB ASB=(1) t10 A[5:0] D[7:0] ACKB DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit t2 t1 ADDRESS t13 t14 110 of 121 t3 t5 t15 t8 t9 WRITE DATA t11 t12 ...
Page 111
... Figure 9-8. Motorola Mux Write Cycle CSB RWB DSB ASB AD[7:0] ADDRESS ACKB DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit t13 t14 111 of 121 t3 t5 t13 t9 WRITE DATA t12 t11 ...
Page 112
... SCLK t6 SDI LSB Figure 9-10. Serial Bus Timing Read Operation with CLKE = SCLK CSB SDO Figure 9-11. Serial Bus Timing Read Operation with CLKE = SCLK CSB SDO DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 9-11.) SYMBOL ...
Page 113
... TPOS, TNEG Hold Time with Respect to TCLK Falling Edge TCLK Pulse-Width High TCLK Pulse-Width Low TCLK Period TCLK Rise Time TCLK Fall Time Figure 9-12. Transmitter Systems Timing DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit SYMBOL MIN ...
Page 114
... Delay RCLK to CV Valid in Single-Rail Mode RCLK Pulse-Width High RCLK Pulse-Width Low RCLK Period Figure 9-13. Receiver Systems Timing 1 RCLK 2 RCLK t1 RPOS,RNEG t2 CV Notes: 1) CLKE = 1. 2) CLKE = 0. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit SYMBOL MIN 200 t4 200 t5 BPV/ EXZ/ CV 114 of 121 TYP MAX ...
Page 115
... Figure 9-14.) PARAMETER TCK Period TMS and TDI Setup to TCK TMS and TDI Hold to TCK TCK to TDO Hold Figure 9-14. JTAG Timing DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit SYMBOL MIN t1 100 115 of 121 TYP ...
Page 116
... RNEG4 D5 N RTIP4 RRING4 D7 GNDT4 P AVDD AVSS RRING5 LOS5 RRING6 LOS7 T RTIP5 LOS6 RTIP6 VDDT5 DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit VDDT16 TTIP16 TTIP15 VDDT15 RTIP15 VDDT14 RSTB TRING16 TRING15 LOS14 RRING15 LOS13 TNEG16 TNEG15 RNEG15 RPOS15 RNEG14 ...
Page 117
... PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 11.1 256-Ball TE-CSBGA (17mm x 17mm) (56-G6028-001) DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit 117 of 121 ...
Page 118
... J1-LBO3 1.95 1.60 J1-LBO4 1.99 1.63 Note 1: Typical voltage, transmitting/receiving 50 Watts. Typical voltage, transmitting/receiving 100 Watts. Note 2: Note 3: Maximum voltage, transmitting/receiving 100 Watts. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit MIN -40°C +16.6°C/W +3.0°C/W +7.5°C/W +15.0°C/W +14.6°C/W +14.0°C/W TYPICAL 100% 1s (Note 2) FULLY PARTIALLY ...
Page 119
... Maximum voltage, transmitting/receiving 100 Watts. ° θ Example: Mode = Typical 100% 1s E1-75 This is below the maximum junction temperature and, therefore, this solution will support the thermal requirements. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit TYPICAL 100% 1s (Note 2) FULLY PARTIALLY EXTERNAL INTERNAL INTERNAL 0.072 0.151 0.125 ...
Page 120
... Reserved to CALEN (see also page 44, Table 6-5). (Page 58) For TST, changed bits 7, 6, and 5 from Reserved to JABWS1, JABWS0, and RHPMC. (Page 60) In the bit 7 (RIMPON) description, changed GC.RTCTL to TST.RHPMC; added note to bit description. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit DESCRIPTION 120 of 121 ...
Page 121
... The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit DESCRIPTION © ...