UPD75518 NEC, UPD75518 Datasheet - Page 116

• Manufacturer Part Number: UPD75518
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC

SCK1
SO1
EOT
116
(2) Three-wire serial I/O mode operations
SI1
The three-wire serial I/O mode is compatible with other modes used in the 75X series, PD7500 series,
and 78K series. This mode is set by setting CSIE1 to 1.
Communication is performed using three lines: Serial clock (SCK1), serial output (SO1), and serial input
(SI1).
The three-wire serial I/O mode transfers data with eight bits as one block. Data is transferred bit by bit
in phase with the serial clock.
Shift register 1 performs shift operation on the falling edge of the serial clock (SCK1). Transmit data is
latched on the SO1 latch, and is output on the SO1 pin. Receive data applied to the SI1 pin is latched in
the shift register 1 on the rising edge of SCK1.
When eight bits have been transferred, operation of shift register 1 automatically terminates setting the
serial transfer end flag (EOT).
Setting the serial transfer and flag (EOT) cannot release the standby function.
Example
To transfer the RAM data specified by the HL register pair to SIO1, load the SIO1 data to the
accumulator, and start serial transfer:
MOV XA, @HL
SEL
XCH
Execution of instruction that writes data to SIO1 (Transfer start request)
MB15
XA, SIO1
Fig. 4-56 Timing of the Three-Wire Serial I/O Mode
1
Transfer is started in phase with falling edge of SCK1.
DO7
DI7
; Fetch transmit data from RAM
; or CLR1 MBE
; Exchange transmit data and receive data, and start transfer
2
DO6
DI6
3
DO5
DI5
4
DO4
DI4
5
DO3
DI3
6
DO2
DI2
7
DO1
DI1
Completion of transfer
8
DO0
DI0
PD75518(A)