LM3S316 Luminary Micro, Inc., LM3S316 Datasheet - Page 40

• Manufacturer Part Number: LM3S316
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

ARM Cortex-M3 Processor Core
40
Reset
Reset
Type
Type
Bit/Field
31:17
15:3
SysTick Control and Status
Address: 0xE000E010
16
2
1
0
RO
RO
31
15
0
0
Register 1: SysTick Control and Status Register
Use the SysTick Control and Status Register to enable the SysTick features.
RO
RO
30
14
0
0
CLKSOURCE
COUNTFLAG
reserved
reserved
ENABLE
TICKINT
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
R/W
R/W
R/W
R/W
RO
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
0
0
0
0
0
0
RO
RO
25
0
9
0
Preliminary
reserved
Description
Reserved bits return an indeterminate value, and should never
be changed.
Returns 1 if timer counted to 0 since last time this was read.
Clears on read by application. If read by the debugger using the
DAP, this bit is cleared on read-only if the MasterType bit in the
AHB-AP Control Register is set to 0. Otherwise, the
COUNTFLAG bit is not changed by the debugger read.
Reserved bits return an indeterminate value, and should never
be changed.
0 = external reference clock. (Not implemented for Stellaris
microcontrollers.)
1 = core clock.
If no reference clock is provided, it is held at 1 and so gives the
same time as the core clock. The core clock must be at least 2.5
times faster than the reference clock. If it is not, the count values
are Unpredictable.
1 = counting down to 0 pends the SysTick handler.
0 = counting down to 0 does not pend the SysTick handler.
Software can use the COUNTFLAG to determine if ever counted
to 0.
1 = counter operates in a multi-shot way. That is, counter loads
with the Reload value and then begins counting down. On
reaching 0, it sets the COUNTFLAG to 1 and optionally pends
the SysTick handler, based on TICKINT. It then loads the Reload
value again, and begins counting.
0 = counter disabled.
reserved
RO
RO
24
0
8
0
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
CLKSOURCE
R/W
RO
18
0
2
0
TICKINT ENABLE
April 27, 2007
R/W
RO
17
0
1
0
COUNTFLAG
R/W
R/W
16
0
0
0