LM3S316 Luminary Micro, Inc., LM3S316 Datasheet - Page 374

• Manufacturer Part Number: LM3S316
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Pulse Width Modulator (PWM)
374
Reset
Reset
Type
Type
Bit/Field
31:14
PWMn Interrupt/Trigger Enable (PWMnINTEN)
7:6
13
12
11
10
9
8
RO
RO
31
15
0
0
reserved
Register 12: PWM0 Interrupt/Trigger Enable (PWM0INTEN), offset 0x044
Register 13: PWM1 Interrupt/Trigger Enable (PWM1INTEN), offset 0x084
These registers control the interrupt and ADC trigger generation capabilities of the PWM
generators (PWM0INTEN controls the PWM generator 0 block, and so on). The events that can
cause an interrupt or an ADC trigger are:
Any combination of these events can generate either an interrupt or an ADC trigger, though no
determination can be made as to the actual event that caused an ADC trigger.
RO
RO
30
14
0
0
TrCntLoad
TrCntZero
TrCmpBD
TrCmpBU
TrCmpAD
TrCmpAU
The counter being equal to the load register
The counter being equal to zero
The counter being equal to the comparator A register while counting up
The counter being equal to the comparator A register while counting down
The counter being equal to the comparator B register while counting up
The counter being equal to the comparator B register while counting down
reserved
reserved
Name
TrCmpBD
R/W
RO
29
13
0
0
TrCmpBU
R/W
RO
28
12
0
0
TrCmpAD
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
27
11
0
0
TrCmpAU TrCntLoad TrCntZero
R/W
RO
26
10
0
0
Reset
R/W
RO
25
0
9
0
0
0
0
0
0
0
0
0
Preliminary
R/W
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
When 1, a trigger pulse is output when the counter matches
the comparator B value and the counter is counting down.
When 1, a trigger pulse is output when the counter matches
the comparator B value and the counter is counting up.
When 1, a trigger pulse is output when the counter matches
the comparator A value and the counter is counting down.
When 1, a trigger pulse is output when the counter matches
the comparator A value and the counter is counting up.
When 1, a trigger pulse is output when the counter matches
the PWMnLOAD register.
When 1, a trigger pulse is output when the counter is 0.
Reserved bits return an indeterminate value, and should
never be changed.
RO
RO
23
0
7
0
reserved
RO
RO
22
0
6
0
IntCmpBD
R/W
RO
21
0
5
0
IntCmpBU
R/W
RO
20
0
4
0
IntCmpAD
R/W
RO
19
0
3
0
IntCmpAU
R/W
RO
18
0
2
0
IntCntLoad
April 27, 2007
R/W
RO
17
0
1
0
IntCntZero
R/W
RO
16
0
0
0