LM3S316 Luminary Micro, Inc., LM3S316 Datasheet - Page 132

• Manufacturer Part Number: LM3S316
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

General-Purpose Input/Outputs (GPIOs)
132
Reset
Reset
Type
Type
Bit/Field
31:8
GPIO Masked Interrupt Status (GPIOMIS)
Offset 0x418
7:0
RO
RO
31
15
0
0
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418
The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect
the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has
been generated, or the interrupt is masked.
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the
ADC. If PB4 is configured as a non-masked interrupt pin (GPIOIM is set to 1), not only is an
interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event
Multiplexer Select (ADCEMUX) register (see page 221) is configured to use the external trigger,
an ADC conversion is initiated.
If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored
Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts
and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt
handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC
interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC
registers until the conversion is completed.
GPIOMIS is the state of the interrupt after masking.
RO
RO
30
14
0
0
reserved
Name
MIS
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
Type
RO
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
0x00
0
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
GPIO Masked Interrupt Status
Masked value of interrupt due to corresponding pin.
0: Corresponding GPIO line interrupt not active.
1: Corresponding GPIO line asserting interrupt.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
MIS
RO
RO
19
0
3
0
RO
RO
18
0
2
0
April 27, 2007
RO
RO
17
0
1
0
RO
RO
16
0
0
0