LM3S101 Luminary Micro, Inc., LM3S101 Datasheet - Page 7

• Manufacturer Part Number: LM3S101
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

List of Figures
Figure 1-1.
Figure 1-2.
Figure 2-1.
Figure 2-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 7-1.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 8-4.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 10-1.
Figure 11-1.
Figure 11-2.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 12-4.
Figure 12-5.
Figure 12-6.
Figure 12-7.
Figure 12-8.
Figure 12-9.
Figure 12-10. MICROWIRE Frame Format (Single Frame)........................................................................... 233
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ............................................................... 234
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements............................ 235
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 14-1.
Figure 17-1.
Figure 17-2.
Figure 17-3.
Figure 17-4.
Figure 17-5.
Figure 17-6.
Figure 17-7.
October 5, 2006
Stellaris High-Level Block Diagram ........................................................................................... 21
LM3S101 Controller System-Level Block Diagram ................................................................... 26
CPU Block Diagram .................................................................................................................. 28
TPIU Block Diagram .................................................................................................................. 29
JTAG Module Block Diagram .................................................................................................... 36
Test Access Port State Machine ............................................................................................... 39
IDCODE Register Format.......................................................................................................... 43
BYPASS Register Format ......................................................................................................... 43
Boundary Scan Register Format ............................................................................................... 44
External Circuitry to Extend Reset............................................................................................. 46
Main Clock Tree ........................................................................................................................ 49
Flash Block Diagram ................................................................................................................. 83
GPIO Module Block Diagram .................................................................................................... 98
GPIO Port Block Diagram.......................................................................................................... 99
GPIODATA Write Example...................................................................................................... 100
GPIODATA Read Example ..................................................................................................... 100
GPTM Module Block Diagram ................................................................................................. 136
16-Bit Input Edge Count Mode Example ................................................................................. 140
16-Bit Input Edge Time Mode Example................................................................................... 141
16-Bit PWM Mode Example .................................................................................................... 142
WDT Module Block Diagram ................................................................................................... 167
UART Module Block Diagram.................................................................................................. 191
UART Character Frame........................................................................................................... 192
SSI Module Block Diagram...................................................................................................... 226
TI Synchronous Serial Frame Format (Single Transfer).......................................................... 228
TI Synchronous Serial Frame Format (Continuous Transfer) ................................................. 229
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................................... 230
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................................. 230
Freescale SPI Frame Format with SPO=0 and SPH=1........................................................... 231
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0............................... 231
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0....................... 232
Freescale SPI Frame Format with SPO=1 and SPH=1........................................................... 232
Analog Comparator Module Block Diagram ............................................................................ 261
Structure of Comparator Unit................................................................................................... 262
Comparator Internal Reference Structure ............................................................................... 263
Pin Connection Diagram.......................................................................................................... 273
Load Conditions....................................................................................................................... 285
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement ................ 287
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer................................. 288
SSI Timing for SPI Frame Format (FRF=00), with SPH=1...................................................... 288
JTAG Test Clock Input Timing................................................................................................. 290
JTAG Test Access Port (TAP) Timing ..................................................................................... 290
JTAG TRST Timing ................................................................................................................. 290
Preliminary
LM3S101 Data Sheet
7