UPD16434 NEC, UPD16434 Datasheet - Page 38

• Manufacturer Part Number: UPD16434
• Description: 1/8/ 1/16 DUTY LCD CONTROLLER/DRIVER
• Manufacturer: NEC

8. RESET OPERATION
initialized contents. In addition, the next processing will be performed at the falling edge of the RESET signal. The display
output will be the same as when the DISP OFF is executed.
38
The
When the high level input to the RESET pin is returned to low, the operation becomes possible, according to the
The chip address compare data (compared with CA1, CA0 inputs) is initialized to 00.
In a single chip configuration, /BUSY output operation is the same as that when CA1 and CA0 are 00.
All processing operations (command/data processing, reading timing signal and display data to the row and
column driver) are stopped.
V
to R7/R15).
The internal functions are set as follows (to the same conditions as when these commands are executed) :
The byte transfer end counter is cleared.
If the
The data memory contents become undefined.
The interface specification code (serial/parallel specification, chip address selection function provided/
unprovided) is read from the D2(CAE) and D1(P, /S) pins.
A chip, whose CA1 and CA0 values are 0, becomes selected state.
When CA1, CA0 = 00
Other than 00
SWM (I
LDPI (D
SMM (M
SFF (F
In a multi-chip configuration, /BUSY output operation will differ, depending on whether CA1 and CA0 of the chip
are 00 (coinciding address) or not (non-coinciding address) (refer to Figure 8–1).
LC3
PD16434 is initialized as follows, when a high level is input to the RESET pin :
level DC current is output from each LCD drive signal output pin (C0 to C41, R15/C42 to R8/C49, R0/R8
2
PD16434 is in the standby mode, the standby mode is maintained.
1
6
I
2
to F
0
to D
to M
= 00)
0
0
= 000)
0
= 0000000) : Data pointer is cleared to 0
= 000)
: Sets /BUSY output to low, if /CS = 0. If /CS = 1, sets /BUSY output to high
: Sets /BUSY output to high impedance, regardless of /CS input.
: Auto-increment mode
: 8-time-divisions, R0/R8 to R7/R15 pins serve as R0 to R7 pins, SYNC pin is set in
: Frame frequency is set to f
impedance.
the input mode, the data memory is set to bank 0.
Data Sheet S10299EJ4V0DS00
CL
/2
14
.
PD16434