IMP706JCSA IMP Inc, IMP706JCSA Datasheet - Page 6

• Manufacturer Part Number: IMP706JCSA
• Description: 3/3.3/4.0V P SUPERVISOR CIRCUITS
• Manufacturer: IMP Inc

RESET/RESET Operation
The RESET/RESET signals are designed to start or return a
µP/µC to a known state.
With V
asserted. During a power-up sequence, the reset outputs remain
asserted until the supply rises above the threshold level. The
resets are deasserted approximately 200ms after crossing the
threshold.
In a brownout situation where V
the reset outputs are asserted. If a brownout occurs during an
already initiated reset period, the reset period will extend for an
additional reset period of 200ms.
The IMP708 devices have dual reset outputs, one active LOW and
one active HIGH. The IMP706P has a single active HIGH reset and
the IMP706/R/S/T/J devices have an active LOW reset output.
Manual Reset (MR)
The active-LOW manual reset input is pulled high by an internal
20kΩ pull-up resistor and can be driven low by CMOS/TTL logic
or a mechanical switch to ground. An external debounce circuit is
unnecessary since the 140ms minimum reset time will debounce
mechanical pushbutton switches. The minimum MR input pulse
6
RESET
IMP706P
IMP706R
IMP706S
IMP706T
IMP706J
IMP708R
IMP708S
IMP708T
IMP708J
WDO
Detail Descriptions
WDI
CC
5V
0V
5V
0V
5V
0V
above 1.2V, RESET and RESET are guaranteed to be
t
WP
Both: HIGH & LOW
Both: HIGH & LOW
Both: HIGH & LOW
Both: HIGH & LOW
HIGH
LOW
LOW
LOW
LOW
Watchdog Timing
t
WD
RESET triggered by MR
CC
falls below the threshold level,
2.63V
2.63V
2.93V
3.08V
4.00V
2.63V
2.93V
3.08V
4.00V
t
WD
408-432-9100/www.impweb.com
Yes
Yes
Yes
Yes
Yes
No
No
No
No
t
WD
IMP706P/R/S/T/J, IMP708R/S/T/J
IMP706P/R/S/T/J, IMP708R/S/T/J
706P_04.eps
width is 0.5µs with a 3V V
input. If not used, tie MR to V
By connecting the watchdog output (WDO) and MR, a watchdog
timeout forces a RESET to be generated.
Watchdog Timer
A watchdog timer available on the IMP706P/R/S/T/J monitors
µP/µC activity. If activity is not detected within 1.6 seconds on the
Watchdog Input (WDI), the internal timer puts the Watchdog
Output (WDO) into a LOW state. WDO will remain LOW until
activity is detected at WDI.
The watchdog function is disabled, meaning it is cleared and not
counting, if WDI is floated or connected to a three-stated circuit.
The watchdog timer is also disabled if RESET is asserted. When
RESET becomes inactive and the WDI input sees a high or low
transition as short as 100ns (V
watchdog timer will begin a 1.6 second countdown. Additional
transitions at WDI will reset the watchdog timer and initiate a
new countdown sequence.
WDO will also become LOW and remain so, whenever the supply
voltage, V
as soon as V
pulse width for WDO as there is for the RESET outputs. If WDI is float-
ed, WDO essentially acts as a low supply voltage output indicator.
Power-failure detection with auxiliary comparator
All devices have an auxiliary comparator with 1.25V trip point.
The output, PFO, is active LOW and the noninverting input is PFI.
This comparator can be used as a supply voltage monitor with an
external resistor voltage divider. As the monitored voltage level
falls, PFI is reduced causing the PFO output to go LOW.
Normally PFO interrupts the processor so the system can be shut
down in a controlled manner.
RESET
WDO
V
MR
CC
5V
0V
5V
0V
5V
0V
5V
0V
CC
, falls below the device threshold level. WDO goes HIGH
CC
transitions above the threshold. There is no minimum
WDI Three-state operation
v
RT
CC
MR externally
CC
CC
input and 0.15µs with a 5V V
set low
or leave floating.
t
RS
= 2.7V)/50ns (V
t
MD
t
MR
CC
t
RS
©
= 4.5V), the
1999 IMP, Inc.
706P_05.eps
CC