IMP1232 IMP Inc, IMP1232 Datasheet - Page 4

• Manufacturer Part Number: IMP1232
• Description: 5V P Power Suppl er Supply Monit y Monitor and or and Reset Cir eset Circuit
• Manufacturer: IMP Inc

Supply Voltage Monitor
Reset Signal Polarity and Output Stage Structure
RESET is an active LOW signal. It is developed with an open
drain driver. If a pullup resistor is required, typical values are
10k to 50k .
RESET is an active High signal developed by a CMOS push-pull
output stage and is the logical opposite to RESET.
Trip Point Tolerance Selection
With TOL connected to V
whenever V
when V
After V
RESET remain active for a minimum time period of 250ms.
On power-down, once V
stays LOW and is guaranteed to be 0.4V or less until V
below 1.2V. The active HIGH reset signal is valid down to a V
level of 1.2V also.
V
4
RESET
RESET
CC
Application Information
V
CC
CC
CC
falls below 4.75V if TOL is connected to ground.
has risen above the trip point set by TOL, RESET and
Figure 2. Timing Diagram: Power Down
CC
Figure 1. Timing Diagram: Power Up
falls below 4.5V. RESET and RESET become active
4.75V
4.25V
V
CCTP
V
V
CC
OH
OL
CC
V
falls below the reset threshold RESET
4.25V
CCTP
, RESET and RESET become active
4.75V
t
F
t
R
t
t
RPD
RPU
V
V
OH
OL
408-432-9100/www.impweb.com
RESET
RESET
1232_05.eps
CC
1232_04.eps
drops
CC
Manual Reset Operation
Push-button switch input, PBRST, allows the user to override the
internal trip point detection circuits and issue reset signals. The
pushbutton input is debounced and is normally pulled HIGH
through an internal 40k resistor.
When PBRST is held LOW for the minimum time t
become active and remain active for approximately a minimum
time period of 250ms after PBRST returns HIGH.
The debounced input is guaranteed to recognize pulses greater
than 20ms. No external pull-up resistor is required, since PBRST
is pulled HIGH by an internal 40k resistor.
The PBRST can be driven from a TTL or CMOS logic line or short-
ed to ground with a mechanical switch.
PBRST
RESET
RESET
T
T
O
O
L
L
=
=
Figure 4. Application Circuit: Pushbutton Reset
Figure 3. Timing Diagram: Pushbutton Reset
V
G
C
N
C
D
1
2
3
4
IMP1232LP/LPS
PBRST
TD
TOL
GND
V
1
5
IL
0
RESET
RESET
%
%
t
PDLY
t
V
PB
ST
CC
IMP1
IMP1
8
7
6
5
4
5V
4
2 .
5 .
5
232LP/LPS
232LP/LPS
4
4
3 .
6 .
7
2
V
IH
t
RESET
RST
PB
©
, both resets
1999 IMP, Inc.
4
4
P
1
4 .
7 .
2
3
V
V
1232_06.eps
2
9
4
_
1232_08.eps
OH
OL
0 t
2
e .
p
s