LS110GXS-1CF269C Lattice Semiconductor Corp., LS110GXS-1CF269C Datasheet - Page 7

• Manufacturer Part Number: LS110GXS-1CF269C
• Description: Fully Integrated 10gbps Serializer/deserializer Device
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Mode 2: Synchronous line loopback with clock clean-up. Driving LB_P622_Enb low enables line loopback
mode. In order to make this loopback mode SONET/SDH compliant the CK622OUT_P/N must be connected to a
VCXO-powered PLL chip (e.g. MAX3670), and CK622OUT_SEL pulled/driven high. The output of the PLL provides
a low jitter reference clock that is in phase with the data presented at the LVDS parallel outputs. This reference
clock is connected to REF_CK_P/N. As in Mode 1 a separate reference clock is input to RX_REF_CK_P/N to drive
the CDR logic. Data on the TX_D_P/N and RX_D_P/N pins are now synchronous, and the data repeated on
TX_D_P/N meets SONET/SDH line loopback application requirements.
Figure 4. Line Loopback Mode 2 Block Diagram
Reference Clocks
There are two AC coupled reference clock input pairs, REF_CK_P/N, and RX_REF_CK_P/N. The CDR block is
driven by either REF_CK_P/N or RX_REF_CK_P/N. The CMU block is only driven by REF_CK_P/N. The reference
clock input frequency for REF_CK_P/N can be either 1/16
data rate. Likewise, RX_REF_CK_P/N can be 1/16
REF_CK_P/N are configured in tandem to 1/16
dently. AC coupling for all reference clocks is recommended.
LB_LVDS_ENb=1
BIST_ENb=0
BIST_LB_SC0=0
BIST_LB_SC1=1
RX_D_LV[0..15]
RX_CK_LV_P/N
LB_P622_ENb=0
TX_D_LV[0..15]
TX_CL_LV_P/N
REF_CK_P/N
CK622_OUT_PN
CK622OUT_SEL = 1
External Low Jitter PLL
LVDS
LVDS
Data
Data
RX
(e.g. MAX 3670)
TX
Reference
PLL
LVDS Loopback
th
Low Jitter Clock
Synchronous to
REF_CK_P/N
1
0
or 1/64
Mode 1
th
or 1/64
To REF_CK_P/N
7
th
1
0
th
by REF_CK_SEL. They cannot be configured indepen-
(622MHz) or 1/64
th
the 10Gbps receiver rate. RX_REF_CK_P/N and
Loopback
Parallel
Deserializer
Serializer
CMU
th
(155MHz) the transmitter/receiver
XPIO 110GXS Data Sheet
10G RX
10G TX
TX_D_N
RX_D_P
RX_D_N
TX_D_P