LS110GXS-1CF269C Lattice Semiconductor Corp., LS110GXS-1CF269C Datasheet - Page 22

• Manufacturer Part Number: LS110GXS-1CF269C
• Description: Fully Integrated 10gbps Serializer/deserializer Device
• Manufacturer: Lattice Semiconductor Corp.

Input and Analog Pin Assignments and Descriptions
Lattice Semiconductor
TX_CK_LV_PA[0]
TX_CK_LV_PA[1]
TX_D_EN
TX_CK622_PA[1]
TX_CK622_PA[0]
PWDN_TXb
PWDN_RXb
RESET_RXb
CK622OUT_SEL
REF_CK_SEL
RX_LV_EN
TX_CP_ISET[1]
TX_CP_ISET[0]
TX_LV_PLLBPb
TX_CK_LV_SEL
BIST ENb
BIST LB SC[1]
TX_CP_ISE[0]
1. All LVCMOS/In pins have built-in pullup resistors.
2. REF_CK is the CDR reference clock when RX_REF_CK_Enb = 1.
Pin Name
LVDS TX clock adjustment for 622 MHz or 311 MHz mode.
10 Gbps CML TX enable.
CLK622 timing adjustment.
TX power down.
RX power down.
RX reset.
CK622 enable.
Ref CLK frequency selection.
LVDS output enable.
TX charge pump current setting.
LVDS PLL bypass. Inverting phase of 622M clock
TX_CK_LV_P/N is used to sample the input parallel data.
Sets TX_CK_LV_P/N frequency.
Enable built-in self test. Used for LVDS loopback.
Configures LVDS loopback
Pin Description
22
1
(Continued)
XPIO 110GXS Data Sheet
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
Function
Flip-chip
R3, M5
D2, E3
Ball #
BGA
N16
G7
G9
C3
P2
N6
P5
R6
P6
P8
R9
E9
E5
J6