DSP56300 Motorola Inc, DSP56300 Datasheet - Page 5

• Manufacturer Part Number: DSP56300
• Description: DSP56301 Digital Signal Processor
• Manufacturer: Motorola Inc

Errata
Number
ED13
ED15
ED17
ED18
ED19
DSP56301 Errata
 1996-2002, Motorola
Document Update
Description (added 5/15/98):
When the HI32 is in PCI mode, the Insert Address Enable control
bit (IAE=1) can be set only with the Receive Buffer Lock Enable
control bit set (RBLE=1 in the DPCR register.)
Description (added 7/21/98):
The DRAM Control Register (DCR) should not be changed while
refresh is enabled. If refresh is enabled only a write operation that
disables refresh is allowed.
Workaround:
First disable refresh by clearing the BREN bit, than change other
bits in the DCR register, and finally enable refresh by setting the
BREN bit.
Description (added 9/28/98):
In all DSP563xx technical datasheets, a note is to be added under
"AC Electrical Characteristics" that although the minimum value
for "Frequency of Extal" is 0MHz, the device AC test conditions are
15MHz and rated speed.
Workaround:
N/A
Description (added 11/2/98):
The PCI host must not change the values of the HBE[3:0] bits
during PCI read transactions from the HI32 as a PCI target.
Description (added 11/9/98):
To guarantee the proper HI32 operation, the DMA should service
the HI32 under the following restrictions:
•
•
Two DMA channels should not service the DRXR FIFO if
master and slave data is mixed there.
The DMA data transfers should not be concurrent with the
56300 Core data transfers to/from the same HI32 data
FIFO.
Freescale Semiconductor, Inc.
DSP56301 Digital Signal Processor
For More Information On This Product,
301CE2K30A_0_8
Go to: www.freescale.com
Mask:2K30A
Chip Errata
ng 12/19/02 pg. 5
Applies
to Mask
2K30A
2K30A
2K30A
2K30A
2K30A