DSP56300 Motorola Inc, DSP56300 Datasheet
DSP56300
Related parts for DSP56300
DSP56300 Summary of contents
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Freescale Semiconductor, Inc. DSP56301 Digital Signal Processor General remark: In order to prevent the use of instructions or sequences of instructions that do not operate correctly, we encourage you to use the “lint563” program to identify such cases and use ...
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Freescale Semiconductor, Inc. DSP56301 Digital Signal Processor Documentation Errata Errata Document Update Number Description (revised 11/9/98): XY memory data move does not work properly if the X-memory move destination is internal I/O and the Y-memory move source is a register ...
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... ED7 DMA Channel 0 (DACT = 1 and DCH[2:0] = 000). Workaround: None. Pertains to: DSP56300 Family Manual, Sections 8.1.6.3 and 8.1.6.4 Description (added 10/09/1997): The timing for HSAK is no longer qualified by the data strobe. The new timing numbers are: a. T318—HSAK assertion from HA0–HA10 and HAEN valid is ED8 30 ...
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Freescale Semiconductor, Inc. DSP56301 Digital Signal Processor Errata Document Update Number Description (added 1/27/98): When the SCI is configured in Synchronous mode, internal clock, and all the SCI pins are enabled simultaneously, an extra pulse of 1 DSP clock length ...
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... First disable refresh by clearing the BREN bit, than change other bits in the DCR register, and finally enable refresh by setting the BREN bit. Description (added 9/28/98): In all DSP563xx technical datasheets, a note added under "AC Electrical Characteristics" that although the minimum value for "Frequency of Extal" is 0MHz, the device AC test conditions are ED17 15MHz and rated speed ...
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Freescale Semiconductor, Inc. DSP56301 Digital Signal Processor Errata Document Update Number Description (added 11/24/98): In the Technical Datasheet Voh-TTL should be listed at 2.4 Volts, not as: ED20 TTL = Vcc-0.4 Workaround: This is a documentation update. Description (added 11/24/98): ...
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... HTXR as long as HDTC is set. New definition: ED25 HDTC is set if SRRQ and MRRQ are cleared (i.e. the host-to-DSP data path is emptied by DSP56300 Core reads) under one of the following conditions: • a non-exclusive PCI write transaction to the HTXR termi- nates or completes • ...
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... DTDx bit in DSTR will be cleared only after two ED26 instruction cycles.” Should be replaced with: “Due to the DSP56300 Core pipeline, after DE bit in DCRx is set, the corresponding DTDx bit in DSTR will be cleared only after three instruction cycles.” Description (added 1/12/99): The PBGA mechanical package drawing in the 56301 and 56305 data sheets is incorrect ...
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Freescale Semiconductor, Inc. DSP56301 Digital Signal Processor Errata Document Update Number Description (added 1/7/1997; identified as Documentation Errata 2/1/99): When two consecutive LAs have a conditional branch instruction at LA-1 of the internal loop, the part does not operate properly. ...
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Freescale Semiconductor, Inc. DSP56301 Digital Signal Processor Errata Document Update Number Description (added 9/12/1997; identified as a Documentation errata 2/1/99): When the ESSI transmits data in the On-Demand mode (i.e., MOD = 1 in CRB and DC[4:0] = $00000 in ...
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Freescale Semiconductor, Inc. DSP56301 Digital Signal Processor Errata Document Update Number Description (added 12/16/98; identified as a Documentation errata 2/1/99): When Stack Extension mode is enabled, a use of the instructions BRKcc or ENDDO inside do loops might cause an ...
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Freescale Semiconductor, Inc. DSP56301 Digital Signal Processor Errata Document Update Number nop_before_label2 label2 ..... ..... label1 .... .... fix_brk_routine move #1,lc jmp ENDDO ------ Original code: do #M,label1 ..... ..... ED33 cont. label2 ..... ..... label1 Will be replaced by: ...
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Freescale Semiconductor, Inc. DSP56301 Digital Signal Processor Errata Document Update Number nop_after_jmp label2 ..... ..... label1 .... .... fix_enddo_routine move #1,lc move #nop_after_jmp,la jmp 2) DO FOREVER loops =================== ED33 cont. BRKcc ----- Original code: do #M,label1 ..... ..... label2 ...
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Freescale Semiconductor, Inc. DSP56301 Digital Signal Processor Errata Document Update Number Will be replaced by: do #M,label1 ..... ..... note: JScc and not Jcc nop_before_label2 label2 ..... ..... ED33 cont. label1 .... .... fix_brk_forever_routine move ssh,x:<..> address (for temporary data) ...
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... Will be replaced by: do #M,label1 ..... ..... ED33 cont. JSR and not JMP nop_after_jmp NOP ..... ..... label2 ..... ..... label1 .... .... fix_enddo_routine Pertains to: DSP56300 Family Manual, Section B-4.2, “General Do Restrictions.” DSP56301 Errata For More Information On This Product, 1996-2002, Motorola Chip Errata Mask:2K30A do forever,label2 ..... ..... ENDDO ..... ..... ..... ..... do forever,label2 ..... ..... ...
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... SSH or SSL (i.e., bset, bclr, bchg, jclr, brclr, jset, brset, btst, bsset, jsset, bsclr, jsclr). Workaround: Add two NOP instructions before the second executed instruction. Pertains to: DSP56300 Family Manual, Appendix B, add a new section called “Stack Extension Enable Restrictions.” Cover all cases. Also, in Section 6.3.11.15, add a cross reference to this new section. DSP56301 Errata For More Information On This Product, ...
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... Port A access. Note that at reset, ED38 the BAT bits are initialized to 00. Pertains to: DSP56300 Family Manual, Port A Chapter (Chapter 9 in Revision 2), description of the BAT[1 –0] bits in the AAR3 - AAR0 registers. Also pertains to the core chapter in device-specific user’ ...
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... If no interrupts before the move is a must, mask the interrupts before the REP. Pertains to: DSP56300 Family Manual, Rev. 2, Section A.3, “Instruction Sequence Restrictions.” DSP56301 Errata For More Information On This Product, 1996-2002, Motorola Chip Errata ...
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... DE is not cleared at the end of the block transfer (DTM = 100 or 101). ED42 Pertains to: DSP56300 Family Manual, Rev. 2, Section 10.4.1.2, “End-of-Block- Transfer Interrupt.” Also, Section 10.5.3.5, “DMA Control Registers (DCR[5–0],” discussion of bits 21 – 19 (DTM bits). DSP56301 Errata For More Information On This Product, ...
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Freescale Semiconductor, Inc. DSP56301 Digital Signal Processor Errata Document Update Number Description (added 12/10/2001): The following sequence gives erroneous results different slave on the bus terminates a transaction (for example, assertion of "stop" Immediately afterwards (no ...
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... The Motorola DSP website has additional documentation updates that can be accessed at the following URL: http://www.motorola-dsp.com/ 4. Information contained in the addendum to the DSP56301 data sheet applies to all members of the DSP56300 core family, as appropriate (i.e, references to the HI32 port do not apply to the DSP56302 and DSP56303). DSP56301 Errata For More Information On This Product, ...