PDSP16116AB0GG Mitel Networks Corporation, PDSP16116AB0GG Datasheet - Page 2

• Manufacturer Part Number: PDSP16116AB0GG
• Description: 16 X 16 Bit Complex Multiplier
• Manufacturer: Mitel Networks Corporation

PDSP16116
2
SYSTEM FEATURES
tem applications.
(21)3(21) Trap
tation, the (21)3(21) operation forms an invalid result because
11 is not representable in the fractional number range. The
PDSP16116 eliminates this problem by trapping the (21)3(21)
operation and forcing the multiplier result to become the most
positive representable number.
The PDSP16116 has a number of features tailored for sys-
In multiply operations using two’s complement fractional no-
NOTES
1. Used only in BFP mode
2. Performs different functions in BFP/Normal modes
3. All supply pins must be connected
XR15:0
Xl15:0
YR15:0
Yl15:0
PR15:0
Pl15:0
CLK
CONX
CONY
ROUND
MBFP
AR15:1 3
Al15:1 3
WTA1:0
WTB1:0
WTOUT1:0
SFTA1:0
SFTR2:0
GWR4:0
OSEL1:0
V
GND
SOBFP
EOPSS
CEX
CEY
OER, OEI
DD
Signal
Input
Input
Input
Input
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Input
Input
Power
Power
Type
16-bit input for real X data
16-bit input for imaginary X data
16-bit input for real Y data
16-bit input for imaginary Y data
16-bit output for real P data
16-bit output for imaginary P data
Clock; new data is loaded on rising edge of CLK
Clock, enable X-port input register
Clock, enable Y-port input register
Conjugate X data
Conjugate Y data
Rounds the real and imaginary results
Mode select (BFP/Normal)
Start of BFP operations (see Note 1)
End of pass (See Note 1)
3 MSBs from real part of A-word (See Note 1)
3 MSBs from imaginary part of A-word (See Note 1)
Word tag from A-word
Word tag from B-word/shift control (See Note 2)
Word tag output (See Note 1)
Shift control for A-word / overflow flag (See Note 2)
Shift control for accumulator result (See Note 1)
Global weighting register contents (See Note 1)
Selects the desired output configuration
Output enables
15V Supply (See Note 3)
0V Supply (See Note 3)
Table 1 Signal descriptions
Description
Complex Conjugation
tion of complex data stream. This operation has traditionally re-
quired an additional ALU to multiply the imaginary component
by -1. The PDSP16116 eliminates this requirement by offering
on-chip complex conjugation of either of the two incoming com-
plex data words with no loss in throughput.
Easy Interfacing
istered l/O for data and control. Data inputs have independent
clock enables and data outputs have independent three state
output enables.
Many algorithms using complex arithmetic require conjuga-
As with all PDSP family members the PDSP16116 has reg-
Tie low
Tie low
Tie low
Tie low
Tie low
Tie low
configuration
Normal
mode