PDSP16116AB0GG Mitel Networks Corporation, PDSP16116AB0GG Datasheet - Page 11

• Manufacturer Part Number: PDSP16116AB0GG
• Description: 16 X 16 Bit Complex Multiplier
• Manufacturer: Mitel Networks Corporation

maximum. Hence, it may be worthwhile to try various universal
exponents and choose the one best suited to the particular ap-
plication.
exponent: the 5-bit GWR applicable to all data words from a
given FFT and a 2-bit WTOUT associated with each individual
dataword. To find the complete exponent for a given word, the
GWR for that FFT must be modified by its WTOUT as shown in
Table 6. The result is the number of places the binary point has
shifted to the right during the course of the FFT.
determine the shift required. This is done by subtracting it from
the universal exponent. The number of places to be shifted is
equal to the difference between the two exponents. The shift
can be implemented in a PDSP1601/A (the shift value is fed
into the SV port).
PDSP1601/As must be used (controlled by the same logic) or a
single PDSP1601/A could be used handling real and imaginary
data on alternate cycles (using the same instructions for both
cycles).
in Fig.8. Only 4-bit data paths are used in calculating the
shift. This means that we must be able to trap very small
values negative of GWR and force a 15-bit right shift in
such cases.
A′, B′, BTOUT
In practice, data output may never approach the theoretical
Data is output from the butterfly processor with a two-part
This value must be compared with the universal exponent to
As FFT data consists of real and imaginary parts, either two
An example of an output normalisation circuit is shown
WTA, WTB
A, B, W,
SOBFP
EOPSS
GWR
CLK
1 1
2
START OF
FIRST PASS
3
4
5
Fig. 7 Use of the BFP control signals
1
NOTES
1. 1 = FIRST CYCLE OF DATA IN PASS
2. n = LAST CYCLE OF DATA IN PASS
6
2
7
3
n
NB It is easier to simply add the word tag to the exponent for the
purpose of determing the shift required, instead of modifying it
according to Table.6. To compensate for this, the universal ex-
ponent may be increased by one.
2
1
n
2
5
UNIVERSAL
EXPONENT
n
4-BIT SUBTRACTOR
n
2
4 n
2
Fig. 8 Output normalisation circuit
WTOUT
4-BIT ADDER
3 n
2
4-BIT MUX
NORMALISED OUTPUT DATA
2
SV PORT
GWR
n
2
1111
1
PDSP1601
C PORT
SIGN
END OF FIRST PASS/
START OF NEXT PASS
(MINIMUM NUMBER OF
LAY CYCLES SHOWN).
PERIOD BETWEEN
OTHER INTERMEDIATE
PASSES IS SIMILAR.
BIT
n
16-BIT DATA
B PORT
1
PDSP16116
2
ASRSV
3
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