ST486DX ST Microelectronics, ST486DX Datasheet - Page 17
ST486DX
Manufacturer Part Number
ST486DX
Description
PROGRAMMING MANUAL
Manufacturer
ST Microelectronics
Datasheet
1.ST486DX.pdf
(34 pages)
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The values found in the I/O trap information fields are specified below for all cases.
Upon SMM entry, the CPU enters the following state:
Table 3 - 2
Table 3 - 3
x: invalid
not an I/O ins.
IN
INS
REP INS
OUT al
OUT ax
OUT eax
OUTSB
OUTSW
OUTSD
REP OUTSB
REP OUTSW
REP OUTSD
CS
EIP
EFLAGS
CR0
DR7
Valid Cases
Valid I/O Trap Cases
SMM Entry State
SMM base specified by SMAR, CS limit is set to 4 GBytes
0000 0000h; Begins execution at the base of SMM memory
0000 0002h; Reset State
6000 0010h; Real Mode, Cache in Write Through
0000 0400h; Traps disabled
P
x
0
0
1
0
0
0
0
0
0
1
1
1
x
0
0
0
1
1
1
1
1
1
1
1
1
I
x
x
x
x
01h
03h
0Fh
01h
03h
0Fh
01h
03h
0Fh
Data Size
I/O Write
ST486DX - SMM SOFTWARE CONSIDERATIONS
x
x
x
x
I/O Address
I/O Address
I/O Address
I/O Address
I/O Address
I/O Address
I/O Address
I/O Address
I/O Address
I/O Write
Address
x
x
x
x
xxxxxxdd
xxxxdddd
dddddddd
xxxxxxdd
xxxxdddd
dddddddd
xxxxxxdd
xxxxdddd
dddddddd
I/O Write
Data
ESI or
EDI
EDI
EDI
EDI
ESI
ESI
ESI
ESI
ESI
ESI
ESI
ESI
ESI
x
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