HT49R50 Holtek Semiconductor Inc, HT49R50 Datasheet - Page 19

• Manufacturer Part Number: HT49R50
• Description: 8-Bit Microcontroller
• Manufacturer: Holtek Semiconductor Inc

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The system quits the HALT mode by an external
reset, an interrupt, an external falling edge sig-
nal on port A, or a WDT overflow. An external re-
set causes device initialization, and the WDT
overflow performs a ²warm reset². After examin-
ing the TO and PD flags, the reason for chip re-
set can be determined. The PD flag is cleared by
system power-up or by executing the ²CLR
WDT² instruction, and is set by executing the
²HALT² instruction. On the other hand, the TO
flag is set if WDT time-out occurs, and causes a
wake-up that only resets the PC (Program
Counter) and SP, and leaves the others at their
original state.
The port A wake-up and interrupt methods can
be considered as a continuation of normal exe-
cution. Each bit in port A can be independently
selected to wake up the device by mask option.
Awakening from an I/O port stimulus, the pro-
gram resumes execution of the next instruc-
tion. On the other hand, awakening from an
interrupt, two sequences may occur. If the re-
lated interrupt is disabled or the interrupt is
enabled but the stack is full, the program re-
sumes execution at the next instruction. But if
the interrupt is enabled, and the stack is not
full, the regular interrupt response takes place.
When an interrupt request flag is set before en-
tering the ²halt² status, the system cannot be
awaken using that interrupt.
If wake-up events occur, it takes 1024 t
tem clock period) to resume normal operation.
In other words, a dummy period is inserted af-
ter the wake-up. If the wake-up results from an
interrupt acknowledgment, the actual inter-
rupt subroutine execution is delayed by more
than one cycle. However, if the Wake-up results
in the next instruction execution, the execution
will be performed immediately after the
dummy period is finished.
All I/O ports maintain their original status.
The PD flag is set but the TO flag is cleared.
LCD driver is still running (if the WDT OSC
or RTC OSC is selected).
SYS
(sys-
19
To minimize power consumption, all the I/O
pins should be carefully managed before enter-
ing the HALT status.
Reset
There are three ways in which reset may occur.
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The WDT time-out during HALT differs from
other chip reset conditions, for it can perform a
²warm reset² that resets only the PC and SP
and leaves the other circuits at their original
state. Some registers remain unaffected during
any other reset conditions. Most registers are
reset to the ²initial condition² once the reset
conditions are met. Examining the PD and TO
flags, the program can distinguish between dif-
ferent ²chip resets².
Note: ²u² means ²unchanged²
RES is reset during normal operation
RES is reset during HALT
WDT time-out is reset during normal
operation
TO
u
0
0
1
1
PD
u
u
0
1
1
RES reset during power-up
RES reset during normal
operation
RES Wake-up HALT
WDT time-out during normal
operation
WDT Wake-up HALT
Reset circuit
RESET Conditions
August 18, 1999
HT49C50