HT49R50 Holtek Semiconductor Inc, HT49R50 Datasheet
HT49R50
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HT49R50 Summary of contents
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Features · Operating voltage: 2.2V~5.2V · 8 input lines · 12 bidirectional I/O lines Two external interrupt input · Two 8-bit programmable timer/event · counter with PFD (programmable fre- quency divider) function · LCD driver with 33 ´ ...
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Block Diagram HT49C50 2 August 18, 1999 ...
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Pin Assignment HT49C50 3 August 18, 1999 ...
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HT49C50 4 August 18, 1999 ...
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Pad Assignment * The IC substrate should be connected to VSS in the PCB layout artwork. HT49C50 5 August 18, 1999 ...
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Pin Description Mask Pin Name I/O Option PA0~PA7 constitute an 8-bit bidirectional input/output port with Schmitt trigger input capability. Each bit on port can be PA0/BZ Wake-up configured as a wake-up input by mask option. PA0~PA3 can be PA1/BZ Pull-high ...
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Absolute Maximum Ratings Supply Voltage........................V -0.3V to 5.5V SS Input Voltage .................V -0. Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi- mum Ratings² may cause substantial damage to the device. Functional ...
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Symbol Parameter I I/O Ports Source Current OH Pull-high Resistance I/O Ports and INT0, INT1 A.C. Characteristics Symbol Parameter f System Clock (Crystal OSC) SYS1 f System Clock (RC OSC) SYS2 Timer I/P Frequency f TIMER (TMR0/TMR1) ...
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Functional Description Execution flow The system clock is derived from either a crys- tal oscillator internally divided into four non-overlapping clocks. One instruc- tion cycle consists of four system clock cycles. Instruction fetching and execution ...
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Location 004H Location 004H is reserved for the external in- terrupt service program. If the INT0 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004H. · ...
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Location 014H Location 014H is reserved for the Time Base interrupt service program Time Base in- terrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 014H. · ...
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RAM mapping Of the two types of functional groups, the special function registers consist of an Indirect address- ing register 0 (00H), a Memory pointer register 0 (MP0;01H), an Indirect addressing register 1 (02H), a Memory pointer register 1 (MP1;03H), ...
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Arithmetic and logic unit - ALU This circuit performs 8-bit arithmetic and logic operations and provides the following func- tions: · Arithmetic operations (ADD, ADC, SUB, SBC, DAA) · Logic operations (AND, OR, XOR, CPL) · Rotation (RL, RR, RLC, ...
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Once an interrupt subroutine is serviced, other interrupts are all blocked (by clearing the EMI bit). This scheme may prevent any further in- terrupt nesting. Other interrupt requests may take place during this interval, but only the in- terrupt request ...
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ROM. Only the contents of the PC is pushed onto the stack. If the contents of the register or of the status register (STATUS) is altered by the in- terrupt service program which ...
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Once the interrupt request flags (RTF, TBF, T0F, T1F, EIF1, EIF0) are all set, they re- main in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a soft- ware instruction recommended that ...
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Watchdog timer - WDT The WDT clock source is implemented by a ded- icated RC oscillator (WDT oscillator in- struction clock (system clock/ real time clock oscillator (RTC oscillator). The timer is designed to prevent a ...
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Time base The time base offers a periodic time-out period to generate a regular internal interrupt. Its 12 time-out period ranges from lected by mask option. If time base time-out oc- curs, the related interrupt ...
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All I/O ports maintain their original status. · The PD flag is set but the TO flag is cleared. · LCD driver is still running (if the WDT OSC or RTC OSC is selected). The system quits the HALT ...
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To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system awakes from the HALT state or during power up. Awaking from the HALT state ...
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The states of the registers are summarized below: Reset Register (Power On) Operation) TMR0 xxxx xxxx uuuu uuuu TMR0C 0000 1--- 0000 1--- TMR1 xxxx xxxx uuuu uuuu TMR1C 0000 1--- 0000 1--- Program Counter 000H 000H MP0 xxxx xxxx ...
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Timer/event counter Two timer/event counters are implemented in the HT49C50. Both of them contain an 8-bit programmable count-up counter. The timer/event count 0 clock source may come from the system clock or system clock/4 or RTC time-out signal or external ...
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Label Bits (TMR0C) ¾ 0~2 Unused bits, read as ²0² To define the TMR0 active edge of timer/event counter TE 3 (0=active on low to high; 1=active on high to low) To enable/disable timer counting TON 4 (0=disabled; 1=enabled) 2 ...
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Label Bits (TMR1C) ¾ 0~2 Unused bits, read as ²0² To define the TMR1 active edge of timer/event counter TE 3 (0= active on low to high; 1= active on high to low) To enable/disable timer counting TON 4 (0= ...
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Input/output ports There are a 12-bit bidirectional input/output port, an 8-bit input port in the HT49C50, labeled PA, PB and PC which are mapped to [12H], [14H] and [16H] of the RAM, respectively. PA0~PA3 can be configured as CMOS (output) ...
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LCD display memory The HT49C50 provides an area of embedded data memory for LCD display. This area is lo- cated from 40H to 60H of the RAM at Bank 1. Bank pointer (BP; located at 04H of the RAM) is ...
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LCD driver output The output number of the HT49C50 LCD driver can be 33´2 or 33´3 or 32´4 by mask option (i.e., 1/2 duty or 1/3 duty or 1/4 duty). The bias type of LCD driver can be ²R² type ...
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LCD driver output (1/4 duty, 1/3 bias, C type) 28 HT49C50 August 18, 1999 ...
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Register Bit No. Label Read/Write Reset RT0 0~2 RT1 R/W RT2 3 ¾ ¾ RTCC (09H) 4 QOSC R/W 5~7 ¾ ¾ Mask option The following shows 18 kinds of mask options in the HT49C50. All these options should be ...
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No. Clock source selection of timer/event counter 0. There are two types of selection: system 10 clock or system clock/4. Clock source selection of timer/event counter 1. There are three types of selection: TMR0 11 overflow, system clock or Time ...
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Application Circuits HT49C50 August 18, 1999 ...
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Instruction Set Summary Mnemonic Arithmetic ADD A,[m] Add data memory to ACC ADDM A,[m] Add ACC to data memory ADD A,x Add immediate data to ACC ADC A,[m] Add data memory to ACC with carry ADCM A,[m] Add ACC to ...
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Mnemonic Rotate RRA [m] Rotate data memory right with result in ACC RR [m] Rotate data memory right RRCA [m] Rotate data memory right through carry with result in ACC RRC [m] Rotate data memory right through carry RLA [m] ...
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Mnemonic Miscellaneous NOP No operation CLR [m] Clear data memory SET [m] Set data memory CLR WDT Clear Watchdog timer CLR WDT1 Pre-clear Watchdog timer CLR WDT2 Pre-clear Watchdog timer SWAP [m] Swap nibbles of data memory SWAPA [m] Swap ...
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Instruction Definition ADC A,[m] Add data memory and carry to the accumulator Description The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+C Affected flag(s) ...
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ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ¬ ACC+[m] Affected flag(s) TC2 TC1 ¾ ¾ ...
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CALL addr Subroutine call Description The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then ...
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CLR WDT1 Preclear watchdog timer Description The TD, PD flags and WDT are all cleared (re-counting from zero), if the other preclear WDT instruction has been executed. Only execution of this in- struction without the other preclear instruction sets the ...
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CPLA [m] Complement data memory and place result in the accumulator Description Each bit of the specified data memory is logically complemented (1¢s comple- ment). Bits which previously contained a one are changed to zero and vice-versa. The complemented result ...
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DECA [m] Decrement data memory and place result in the accumulator Description Data in the specified data memory is decremented by one, leaving the result in the accumulator. The contents of the data memory remain unchanged. Operation ACC ¬ [m]-1 ...
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JMP addr Directly jump Description The contents of the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Operation PC ¬ addr Affected flag(s) TC2 TC1 ¾ ¾ MOV A,[m] Move data memory ...
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OR A,[m] Logical OR accumulator with data memory Description Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²OR² ...
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RET A,x Return and place immediate data in the accumulator Description The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Operation PC ¬ Stack ACC ¬ x Affected flag(s) TC2 TC1 ...
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RLC [m] Rotate data memory left through carry Description The contents of the specified data memory and the carry flag are rotated one bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit ...
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RRA [m] Rotate right-place result in the accumulator Description Data in the specified data memory is rotated one bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory ...
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SBC A,[m] Subtract data memory and carry from the accumulator Description The contents of the specified data memory and the complement of the carry flag aresubtractedfromtheaccumulator,leaving the result in theaccumulator. Operation ACC ¬ ACC+[m]+C Affected flag(s) TC2 TC1 ¾ ¾ ...
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SET [m] Set data memory Description Each bit of the specified data memory is set to one. Operation [m] ¬ FFH Affected flag(s) TC2 TC1 ¾ ¾ SET [m].i Set bit of data memory Description Bit ²i² of the specified ...
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SNZ [m].i Skip if bit ²i² of the data memory is not zero Description If bit ²i² of the specified data memory is not zero, the next instruction is skipped. If bit ²i² of the data memory is not zero, ...
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SWAP [m] Swap nibbles within the data memory Description The low-order and high-order nibbles of the specified data memory (one of the data memories) are interchanged. Operation [m].3~[m].0 « [m].7~[m].4 Affected flag(s) TC2 TC1 ¾ ¾ SWAPA [m] Swap data ...
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SZ [m].i Skip if bit ²i² of the data memory is zero Description If bit ²i² of the specified data memory is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced ...
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XORM A,[m] Logical XOR data memory with the accumulator Description Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The zero flag is affected. Operation [m] ...
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... RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright Ó 1999 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are ...