HT46RB50 Holtek Semiconductor, HT46RB50 Datasheet - Page 30

• Manufacturer Part Number: HT46RB50
• Description: A/D Type USB 8-Bit MCU
• Manufacturer: Holtek Semiconductor

There are some timing constrains and usages illustrated here. By setting the MISC register, MCU can perform reading,
writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writing
and clearing.
Note:
Note:
Options
The following table shows all kinds of options in the microcontroller. All of the OTP options must be defined to ensure a
proper functioning system.
Rev. 1.10
Read FIFO0 sequence
Write FIFO0 sequence
Check whether FIFO0 can be read or not
Check whether FIFO0 can be written or not
Read 0-sized packet sequence form FIFO0
Write 0-sized packet sequence to FIFO0
Bit No.
4~7
No.
0
1
2
3
1
2
3
4
5
6
*: There are 2 s existing between 2 reading action or between 2 writing action
*USB definition: when the host sends a set Configuration , the Data pipe should send the DATA0 (Data tog-
gle) first. So, when the device receives a set configuration setup command, user needs to toggle this bit so
the next data will send a Data0 first.
**Needs to set the data pipe as an input pile or output pile. The purpose of this function is to avoid the host from
abnormally sending only an IN or OUT token and disables the endpoint.
DATATG*
PA0~PA7 pull-high resistor enable or disable (by bit)
PB0~PB7 pull down resistor enable or disable (by bit)
PC0~PC7 pull-high resistor enable or disable (by nibble)
PD0~PD7 pull-high resistor enable or disable (by nibble)
PE0~PE5 pull-high resistor enable or disable (by nibble)
LVR enable or disable
SETIO1**
SETIO2**
SETIO3**
Label
SETIO Register (27H), USB Endpoint 1~Endpoint5 Set IN/OUT Pipe Register
Actions
R/W
R/W
R/W
R/W
R/W
To toggle this bit, all the DATA token will send a DATA0 first.
Set endpoint 1 input or output pile (1/0), default input pipe (1)
Set endpoint 2 input or output pile (1/0), default input pipe (1)
Set endpoint 3 input or output pile (1/0), default input pipe (1)
Undefined bit, read as 0
Read or Write FIFO Table
00H 01H delay 2 s, check 41H read* from FIFO0 register and
check not ready (01H) 03H 02H
02H 03H delay 2 s, check 43H write* to FIFO0 register and
check not ready (03H) 01H 00H
00H 01H delay 2 s, check 41H (ready) or 01H (not ready) 00H
02H 03H delay 2 s, check 43H (ready) or 03H (not ready) 02H
00H 01H delay 2 s, check 81H read once (01H) 03H 02H
02H 03H delay 2 s, check 03H 07H 06H 00H
30
Option
MISC Setting Flow and Status
Function
September 7, 2006
HT46RB50