HT46RB50 Holtek Semiconductor, HT46RB50 Datasheet - Page 12

• Manufacturer Part Number: HT46RB50
• Description: A/D Type USB 8-Bit MCU
• Manufacturer: Holtek Semiconductor

Power Down Operation - HALT
The HALT mode is initialized by the HALT instruction
and results in the following:
The system can quit the HALT mode in many ways, by
an external reset, an interrupt, an external falling edge
signal on Port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a warm reset . After examining the TO and PDF
flags, the cause for a chip reset can be determined. The
PDF flag is cleared by a system power-up or by execut-
ing the CLR WDT instruction and is set when execut-
ing the HALT instruction. On the other hand, the TO
flag is set if the WDT time-out occurs, and causes a
wake-up that only resets the Program Counter and SP;
and leaves the others in their original status.
The Port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in Port A can be independently selected to wake-up the
device by option. Awakening from an I/O port stimulus,
the program will resume execution of the next instruc-
tion. If it awakens from an interrupt, two sequences may
occur. If the related interrupt is disabled or the interrupt
is enabled but the stack is full, the program will resume
execution at the next instruction. But if the interrupt is
enabled and the stack is not full, a regular interrupt re-
sponse takes place. When an interrupt request flag is
set to 1 before entering the HALT mode, the wake-up
function of the related interrupt will be disabled. If a
wake-up event occurs, it takes 1024 f
Rev. 1.10
The system oscillator is turned off but the WDT oscil-
lator keeps running (if the WDT oscillator or the real
time clock is selected).
The contents of the on-chip RAM and registers remain
unchanged.
The WDT will be cleared and start recounting (if the
WDT clock source is from the WDT oscillator or the
real time clock).
All of the I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
SYS
(system clock
Watchdog Timer
12
period) to resume normal operation. In other words, a
dummy period is inserted after wake-up. If the wake-up
results from an interrupt acknowledge, the actual inter-
rupt subroutine execution is delayed by more than one
cycle. However, if the wake-up results in the next in-
struction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset may occur:
The WDT time-out during HALT differs from other chip
reset conditions, for it can perform a warm reset that
resets only the Program Counter and SP, leaving the
other circuits in their original state. Some registers re-
main unaffected during any other reset conditions. Most
registers are reset to the initial condition when the re-
set conditions are met. Examining the PDF and TO
flags, the program can distinguish between different
Note: u stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem awakes from the HALT state or during power up.
chip resets .
TO PDF
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
0
u
0
1
1
0
u
1
u
1
RES reset during power-up
RES reset during normal operation
RES wake-up at HALT
WDT time-out during normal operation
WDT wake-up at HALT
RESET Conditions
September 7, 2006
HT46RB50