HT48R02N Holtek Semiconductor, HT48R02N Datasheet - Page 45

• Manufacturer Part Number: HT48R02N
• Description: (HT4xR0xx) Small Package 8-Bit OTP MCU
• Manufacturer: Holtek Semiconductor

www.DataSheet4U.com
The ADCR control register also contains the
PCR3~PCR0 bits which determine which pins on
PA0~PA3 are used as analog inputs for the A/D converter
and which pins are to be used as normal I/O pins. Note
that if the PCR3~PCR0 bits are all set to zero, then all the
PA0~PA3 pins will be setup as normal I/Os.
The START bit in the register is used to start and reset
the A/D converter. When themicrocontroller sets this bit
from low to high and then low again, an analog to digital
conversion cycle will be initiated. When the START bit is
brought from low to high but not low again, the EOCB bit
in the ADCR register will be set to a 1 and the analog
to digital converter will be reset. It is the START bit that is
used to control the overall start operation of the internal
analog to digital converter.
The EOCB bit in the ADCR register is used to indicate
when the analog to digital conversion process is com-
plete. This bit will be automatically set to 0 by the
microcontroller after a conversion cycle has ended. In
addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the inter-
rupts are enabled, an appropriate internal interrupt sig-
nal will be generated. This A/D internal interrupt signal
will direct the program flow to the associated A/D inter-
nal interrupt address for processing. If the A/D internal
interrupt is disabled, the microcontroller can be used to
Rev.1.00
ACSR Register
Bit 7
Bit 6
Bit 5~3
Bit 2~0
Name
POR
R/W
Bit
TEST
TEST: for test mode use only
ADONB: ADC module power on/off control bit
0: ADC module power on
1: ADC module power off
Note: 1. it is recommended to set ADONB=1 before entering sleep for saving power.
unimplemented, read as 0
ADCS2~ADCS0 : Select A/D converter clock source
000: system clock/2
001: system clock/8
010: system clock/32
011: undefined, can t be used.
100: system clock
101: system clock/4
110: system clock/16
111: undefined, can t be used.
R/W
7
1
2. ADONB=1 will power down the ADC module.
ADONB
R/W
6
0
5
45
4
poll the EOCB bit in the ADCR register to check whether
it has been cleared as an alternative method of detect-
ing the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates
from the system clock f
ratio, the value of which is determined by the ADCS2,
ADCS1 and ADCS0 bits in the ACSR register.
Controlling the power on/off function of the A/D con-
verter circuitry is implemented using the value of the
ADONB bit.
Although the A/D clock source is determined by the sys-
tem clock f
there are some limitations on the maximum A/D clock
source speed that can be selected. As the minimum value
of permissible A/D clock period, t
taken for system clock speeds equal to or greater than
4MHz. For example, the system clock operates at a fre-
quency of 4MHz, the ADCS2, ADCS1 and ADCS0 bits
should not be set to 100 . Doing so will give A/D clock pe-
riods that are less than the minimum A/D clock period
which may result in inaccurate A/D conversion values. Re-
fer to the following table for examples, where values
marked with an asterisk * show where, depending upon
the device, special care must be taken, as the values may
be less than the specified minimum A/D Clock Period.
3
SYS
, and by bits ADCS2, ADCS1 and ADCS0,
ADCS2
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
R/W
2
0
SYS
, is first divided by a division
AD
ADCS1
, is 0.5 s, care must be
R/W
1
0
December 15, 2009
ADCS0
R/W
0
0