74HCT7030N,112 NXP Semiconductors, 74HCT7030N,112 Datasheet - Page 14

• Manufacturer Part Number: 74HCT7030N,112
• Description: IC 9X64 FIFO REGISTER 3ST 28-DIP
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT7030N,112

• Package / Case: 28-DIP (0.600", 15.24mm)
• Function: Asynchronous, Synchronous
• Memory Size: 576 (9 x 64)
• Data Rate: 33MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Through Hole
• Logic Family: HCT
• Number Of Circuits: 1
• Maximum Clock Frequency: 36 MHz
• High Level Output Current: - 6 mA
• Low Level Output Current: 6 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 4.5 V
• Logic Type: CMOS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Access Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2901-5; 933798890112

Philips Semiconductors
With FIFO empty; SO is held HIGH in anticipation
Shift-in operation; high-speed burst mode
December 1990
9-bit x 64-word FIFO register; 3-state
(1) HC : V
Fig.10 Waveforms showing ripple through delay SI input to DOR output,
In the high-speed mode, the burst-in rate is determined by the minimum shift-in HIGH and shift-in LOW
specifications. The DIR status flag is a don’t care condition, and a shift-in pulse can be applied regardless of
the flag. A SI pulse which would overflow the storage capacity of the FIFO is ignored.
(1) HC : V
Fig.11 Waveforms showing SI minimum pulse width and SI maximum pulse frequency, in high-speed shift-in
HCT: V
HCT: V
DOR output pulse width and propagation delay from the DOR
pulse to the Q
burst mode.
M
M
M
M
= 50%; V
= 50%; V
= 1.3 V; V
= 1.3 V; V
I
I
I
I
= GND to V
= GND to V
= GND to 3 V.
= GND to 3 V.
n
output.
CC
CC
.
.
14
Notes to Fig.10
1. FIFO is initially empty, SO is held
2. SI pulse; loads data into FIFO
3. DOR flag signals the arrival of
4. Output transition; data arrives at
5. DOR goes LOW; FIFO is empty
6. SO set LOW; necessary to
HIGH.
and initiates ripple through
process.
valid data at the output stage.
output stage after the specified
propagation delay between the
rising edge of the DOR pulse to
the Q
again.
complete shift-out process. DOR
remains LOW, because FIFO is
empty.
n
74HC/HCT7030
output.
Product specification