LMX2331A National Semiconductor, LMX2331A Datasheet - Page 10

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LMX2331A

Manufacturer Part Number
LMX2331A
Description
PLLatinum Dual Frequency Synthesizer for RF Personal Communications
Manufacturer
National Semiconductor
Datasheet

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Functional Description
The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and the 15- and 18-bit N Counters (in-
termediate latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATA register, MSB first. The
data stored in the shift register is loaded into one of 4 appropriate latches on the rising edge of LE. The last two bits are the Con-
trol Bits. The DATA is transferred into the counters as follows:
PROGRAMMABLE REFERENCE DIVIDERS (IF AND RF R COUNTERS)
If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22-bit shift register into a latch which sets
the 15-bit R Counter. Serial data format is shown below.
15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
Notes:
Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 32767
R1 to R15: These bits select the divide ratio of the programmable reference divider.
Data is shifted in MSB first.
Divide
32767
Ratio
3
4
15
R
0
0
1
14
C1
Control Bits
R
0
0
1
0
0
1
1
13
R
0
0
1
12
R
0
0
1
C2
0
1
0
1
11
R
0
0
1
10
10
R
0
0
1
DATA Location
RF R Counter
RF N Counter
IF R Counter
IF N Counter
R
9
0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 1 0 0
1 1 1 1 1 1 1 1 1
R
8
• • • • • • • •
R
7
R
6
R
5
R
4
R
3
R
2
DS012331-14
R
1
DS012331-1

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