CY7C4261V-15JXC Cypress Semiconductor Corp, CY7C4261V-15JXC Datasheet - Page 7

• Manufacturer Part Number: CY7C4261V-15JXC
• Description: IC SYNC FIFO MEM 16KX9 32-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4261V-15JXC

• Access Time: 10ns
• Memory Size: 144K (16K x 9)
• Package / Case: 32-PLCC
• Function: Synchronous
• Data Rate: 100MHz
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Data Bus Width: 9 bit
• Bus Direction: Unidirectional
• Timing Type: Synchronous
• Organization: 16 K x 9
• Maximum Clock Frequency: 66.7 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 25 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Width-Expansion Configuration
Word width may be increased simply by connecting the
corresponding input controls signals of multiple devices. A
composite flag should be created for each of the end-point status
flags (EF and FF). The partial status flags (PAE and PAF) can be
detected from any one device.
word width by using two CY7C42x1Vs. Any word width can be
attained by adding additional CY7C42x1Vs.
When the CY7C42x1V is in a Width-Expansion Configuration,
the Read Enable (REN2) control input can be grounded (see
Figure
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Document #: 38-06013 Rev. *F
Write Enable 2/Load
Write Enable (WEN1)
Programmable (PAF)
Data
Write Clock (WLCK)
2). In this configuration, the Write Enable 2/Load
Full Flag (FF) # 1
Full Flag (FF) # 2
In (D)
(WEN2/LD)
Figure 2. Block Diagram of 16 K / 32 K / 64 K / 128 K × 9 Low-Voltage Deep Sync FIFO Memory
18
9
Read Enable 2 (REN2)
FF
Figure 2
CY7C4261V
CY7C4271V
CY7C4281V
CY7C4291V
Reset (RS)
demonstrates a 18-bit
Used in a Width-Expansion Configuration
EF
9
9
Read Enable 2 (REN2)
Flag Operation
The CY7C4261/71/81/91V devices provide five flag pins to
indicate the condition of the FIFO contents. Empty, Full, PAE,
and PAF are synchronous.
Full Flag
The Full Flag (FF) will go LOW when the device is full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN1 and WEN2/LD. FF is synchronized to WCLK, i.e.,
it is exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW, regardless
of the state of REN1 and REN2. EF is synchronized to RCLK,
i.e., it is exclusively updated by each rising edge of RCLK.
FF
CY7C4261V
CY7C4271V
CY7C4281V
CY7C4291V
Reset (RS)
EF
Empty Flag (EF) #2
Empty Flag (EF) #1
9
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Read Clock
Read Enable 1 (REN1)
Output
Programmable
Data Out (Q)
Enable (OE)
(RCLK)
(PAE)
18
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