CY7C4285V-10ASC Cypress Semiconductor Corp, CY7C4285V-10ASC Datasheet - Page 2

• Manufacturer Part Number: CY7C4285V-10ASC
• Description: IC DEEP SYN FIFO 64KX18 64LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4285V-10ASC

• Function: Synchronous
• Memory Size: 1.1K (64 x 18)
• Data Rate: 100MHz
• Access Time: 8ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1242

Pin Configuration
Functional Description
The CY7C4255/65/75/85V provides five status pins. These
pins are decoded to determine one of five states: Empty, Al-
most Empty, Half Full, Almost Full, and Full (see Table 2). The
Half Full flag shares the WXO pin. This flag is valid in the
stand-alone and width-expansion configurations. In the depth
expansion, this pin provides the expansion out (WXO) infor-
mation that is used to signal the next FIFO when it will be
activated.
Selection Guide
Document #: 38-06012 Rev. *A
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (I
Density
Package
CC1
) (mA)
Commercial
Industrial
(continued)
64-pin 10x10 TQFP
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
15
14
13
12
11
10
9
5
1
8
7
6
4
3
2
0
CY7C4255V
8K x 18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
7C4255/65/75/85V-10
CY7C4255V
CY7C4265V
CY7C4275V
CY7C4285V
64-pin 10x10 TQFP
100
3.5
Top View
10
30
8
0
8
STQFP
CY7C4265V
16K x 18
The Empty and Full flags are synchronous, i.e., they change
state relative to either the read clock (RCLK) or the write clock
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag archi-
tecture guarantees that the flags will remain valid from one
clock cycle to the next. The Almost Empty/Almost Full flags
become synchronous if the V
configurations are fabricated using an advanced 0.35
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
7C4255/65/75/85V-15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64-pin 10x10 TQFP
CY7C4275V
66.7
10
15
10
30
35
4275V–3
4
0
32K x 18
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Q
Q
GND
Q
Q
V
Q
Q
GND
Q
Q
Q
Q
GND
Q
V
CC
CC
14
13
12
11
10
9
8
7
6
5
4
CC
/SMODE is tied to V
7C4255/65/75/85V-25
64-pin 10x10 TQFP
CY7C4285V
64K x 18
40
15
25
15
30
6
1
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