CY7C4285V-25ASC Cypress Semiconductor Corp, CY7C4285V-25ASC Datasheet
CY7C4285V-25ASC
Specifications of CY7C4285V-25ASC
Related parts for CY7C4285V-25ASC
CY7C4285V-25ASC Summary of contents
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... High speed, low power, first-in first-out (FIFO) memories ■ (CY7C4255V) ■ 16K x 18 (CY7C4265V) ■ 32K x 18 (CY7C4275V) ■ 64K x 18 (CY7C4285V) ■ 0.35 micron CMOS for optimum speed and power ■ High speed 100 MHz operation (10 ns read/write cycle times) ■ Low power ❐ ...
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... THREE-ST ATE OUTPUT REGISTER LOGIC – 17 Figure 1. Pin Diagram - 64-Pin STQFP Top View CY7C4255V 7 CY7C4265V 8 9 CY7C4275V 10 11 CY7C4285V CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V FLAG PROGRAM REGISTER FF EF FLAG PAE LOGIC PAF SMODE READ POINTER READ CONTROL 4275V–1 RCLK REN GND ...
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... OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state. Dual Mode Pin: Asynchronous Almost Empty/Almost Full flags – tied to V Synchronous Almost Empty/Almost Full flags – tied to V (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V /SMODE is tied ...
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... EF is LOW, regardless of the state of REN synchronized to RCLK, that is outputs even exclusively updated by each rising edge of RCLK. 0–17 CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V during a program write 0–15 is written into the Empty 0–15 Table 2). All offset registers do not have to be ...
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... Notes Empty Offset (Default Values: CY7C4255/65/75/85V n = 127 Full Offset (Default Values: CY7C4255/65/75/85V n = 127). Document #: 38-06012 Rev. *B CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V the flags have been programmed, the PAF or PAE is asserted, signifying that the FIFO is either Almost Full or Almost Empty. See Table 3 for a description of programmable flags. ...
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... RESET (RS) 18 7C4255V 7C4255V 7C4265V 7C4265V 7C4275V 7C4275V 7C4285V 7C4285V FIRST LOAD (FL) WRITE EXPANSION IN (WXI) READ EXPANSION IN (RXI) CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE) PROGRAMMABLE (PAF) EMPTY FLAG (EF) EF DATA OUT ( 4275V–24 Figure 3 Page [+] Feedback ...
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... PAF PAE WXI RXI READ CLOCK (RCLK) WXO RXO READ ENABLE (REN) 7C4255V 7C4265V OUTPUT ENABLE (OE) 7C4275V 7C4285V FF EF PAE PAF WXI RXI FIRST LOAD (FL) CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V DATA OUT (Q) EF PAE 4275V–25 Page [+] Feedback ...
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... IH < V < Com’l 30 Ind Com’l 4 Ind Test Conditions = 25° MHz 3.3V CC CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V [6] AmbientTemperature V CC 0°C to +70°C 3.3V ±300 mV –40°C to +85°C 3.3V ±300 mV 7C4255/65/75/ 7C4255/65/75/ 85V-15 85V-25 Unit Min Max Min Max 2.4 2 ...
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... Min Max Min 100 4.5 4.5 3 [15 CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V [12, 13] ALL INPUT PULSES 90% 90% 10% 10% ≤ 4287V–5 200 Ω 2.0V ALL INPUT PULSES 90% 90% 10% 10% ≤ 4275V–7 Max Min Max 66 ...
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... Write Clock for Programmable Almost Empty and Programmable Almost Full Flags (Synchronous Mode only) Note 16 after program register write are valid until PAFasynch PAEasynch Document #: 38-06012 Rev. *B 7C4255/65/75/85V-10 7C4255/65/75/85V-15 7C4255/65/75/85V-25 Min Max Min [15 4.5 6 PAF(E) CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V Unit Max Min Max ...
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... NO OPERATION t REF VALID DATA t OE [18] t SKEW2 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V NO OPERATION t WFF REF t OHZ Page [+] Feedback ...
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... The first word is always available the cycle after EF goes HIGH. Document #: 38-06012 Rev. *B [19] Figure 8. Reset Timing RSR t RSF t RSF t RSF [21] t FRL t REF OLZ When t < minimum specification, t CLK SKEW2 SKEW2 CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V [20] OE=1 OE [22 (maximum) = either 2 FRL CLK SKEW2 CLK Page [+] Feedback ...
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... SKEW1 D – WFF FF WEN RCLK t ENH t ENS REN LOW DATA IN OUTPUT REGISTER Q – Document #: 38-06012 Rev. *B CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V Figure 10. Empty Flag Timing ENS t t REF REF t A Figure 11. Full Flag Timing [17 SKEW1 DATA WRITE t WFF t ENS DATA READ D1 t ENH ...
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... Figure 13. Programmable Almost Empty Flag Timing t CLKH WCLK WEN [23] PAE RCLK REN Note 23. PAE is offset = n. Number of data words into FIFO already = n. Document #: 38-06012 Rev. *B CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V Figure 12. Half Full Timing t CLKL t t ENS ENH t HF HALF FULL + 1 OR MORE t ...
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... CY7C4275V, and 65536 − for the CY7C4285V. 28. PAF is offset = m. 29. 8192 − m words in CY7C4255V, 16384 − m words in CY7C4265V, 32768 − m words in CY7C4275V, and 65536 − m words in CY7C4285V. 30. 8192 − words in CY7C4255V, 16384 − words in CY7C4265V, 32768 − words in CY7C4275V, and 65536 − words in CY7C4285V. Document #: 38-06012 Rev ...
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... ENS Figure 17. Write Programmable Registers t CLKL t ENH t DH PAF OFFSET , then PAF may not change state until the next WCLK rising edge. CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V FULL– M WORDS [29] IN FIFO [32] t PAF synch SKEW3 t t ENS ENH PAE OFFSET – ...
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... Read from Last Physical Location. Document #: 38-06012 Rev. *B Figure 18. Read Programmable Registers t CLKL t ENH t A UNKNOWN PAE OFFSET Figure 19. Write Expansion Out Timing Figure 20. Read Expansion Out Timing Figure 21. Write Expansion In Timing XIS CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V PAF OFFSET PAE OFFSET Page [+] Feedback ...
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... The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags are valid at t 37. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t Document #: 38-06012 Rev. *B Figure 22. Read Expansion In Timing XIS [35, 36, 37] Figure 23. Retransmit Timing t PRT to update these flags. RTR CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V t RTR . RTR Page [+] Feedback ...
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... Thin Quad Flat Pack ( 1.4 mm) (Pb-Free) 64-Pin Thin Quad Flat Pack ( 1.4 mm) 51-85051 64-Pin Thin Quad Flat Pack ( 1.4 mm) (Pb-Free) 51-85051 64-Pin Thin Quad Flat Pack ( 1.4 mm) CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V Operating Range Commercial Commercial Industrial Commercial Operating Range Commercial ...
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... Package Diagrams Figure 24. 64-Pin Thin Plastic Quad Flat Pack ( 1.4 mm) Document #: 38-06012 Rev. *B CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V 51-85051 *A Page [+] Feedback ...
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... Document History Page Document Title: CY7C4255V/CY7C4265V/CY7C4275V/CY7C4285V 32K/64Kx18 Low Voltage Deep Sync FIFOs Document Number: 38-06012 Orig. of Submission REV. ECN Change ** 106473 SZV *A 122264 RBI *B 2556036 VKN/AESA Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...