STLC5432 ST Microelectronics, STLC5432 Datasheet - Page 28

• Manufacturer Part Number: STLC5432
• Description: 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE
• Manufacturer: ST Microelectronics

STLC5432
Figure 5: Main Alarm Processing
Figure 6: DIN and DOUT During Time slot 0.
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Serial Interface
Time Slot 0:
P0 + P1 = 0
messages
messages
Dout pin
receives
delivers
RECEIVING
Din pin
DETECTED
During
ALARMS
and
WER
LOS
LOF
915
AIS
AR
LINE STATE
IF TSOE = 0 (CR5)
During Time Slot 0:
Dout pin is High Z.
IF TSOE = 1
During Time Slot 0:
Dout pin delivers consecutively:
ODD = 1 The contents of 31 Time Slots is related to
odd frame received from the line.
ODD = 0 The contents of 31 Time Slots is related to
even frame received from the line. (See Figure 6a).
Din pin receives eight bits:
ODD
TRANSMITTED
X
ODD TS0
ALARMS
BIT 3
SKIP
Ax
SA pin: 0V
X
Parallel Interface: P0 + P1 # 0
SLC
X
Sa4R Sa5R Sa6R Sa7R Sa8R
Sa4E
Sa5E
or
Sa6E
Sa7E Sa8E
and
During Time Slot 0:
Dout pin delivers eight alarms
Din pin is ignored during Time Slot 0
SLC
SKIP
(TSOXR)
AE Bit
MERA
(CR1)
AR
MFNR
REGISTERS
Stand Alone
SA pin: 5V
REGISTER
ALARMS
ALR
Bit 0
Bit 1
Bit 2
Bit 3
Bit 5
LOF
D93TL050B
B
COMPLEM.
REGISTER
ALARM
AIS
CAR1
Bit 0
D93TL051E
LOS