STLC5432 ST Microelectronics, STLC5432 Datasheet
STLC5432
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STLC5432 Summary of contents
Page 1
... The receive circuit performances exceed CCITT recommendation and the line driver outputs meet the G.703 specifications. STLC5432 is the real single chip solution that al- lows the best system flexibility and easy design. STLC5432 can work either in 2048 or 4096 or 8192 Kbit/s systems programming the CR4 regis- ter (when parallel micro interface selected) ...
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... STLC5432 PIN DESCRIPTION Name Pin Type VCCD1 18 I Positive power supply inputs for the digital (V VCCD2 17 I microprocessor interface signals (V VCCA 34 I connected together. GNDD 1 I Negative power supply pins which must be connected together close to the device. All GNDA 44 I digital and analog signals are referred to these pins, which are normally at the system ground ...
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... Frame and Multiframe lost, AIS Alarm Indication Signal is detected. 0Volt 0Volt Frame and Multiframe lost, AIS Alarm Indication Signal is not detected Microprocessor Interface ----------------------------------------------------------------------------------- 0 0 Serial Microprocessor Interface 0 1 ST9 Microprocessor Interface 1 0 Multiplexed Motorola processor interface 1 1 Multiplexed Intel processor interface STLC5432 3/46 ...
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... STLC5432 BLOCK DIAGRAM 4/46 ...
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... LI2 with the equalizer not connected Relative to LI1/LI2 pins with fixed detection threshold 75 at transformer secondary 120 at transformer secondary 75 or 120 at transformer secondary % nominal amplitude at 50% of peak amplitude Filter 20Hz - 100KHz Filter 700Hz - 100KHz STLC5432 Value Unit GND 100 -65 to +150 C ...
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... STLC5432 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter POWER CONSUMPTION Icc75 Active Current (including line current) Icc120 Active Current (including line current) TRANSFORMER SPECIFICATION FOR 75 L:M:N: Turns ratioes RL L Windings Resistance RMN M and N winding resistances LL Inductance of winding L Ls Leakage inductange of a winding, the other being short ...
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... Figure 1: Receiver Diagram STLC5432 7/46 ...
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... This single chip CMOS Device interfaces the physical multiplex of the application to the physi- cal CEPT transmission link at 2048kb/s. STLC5432 contains analog and digital functions to implement line interface function and frame synchronization. It meets pulse shape and jitter specifications in accordance with CCITT Recom- mendations and CEPT standards ...
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... STLC5432 can directly interface binary data stream by means of the 6 dedicated pins: BRDO, RCLO, BRDI, RCLI, BXDO and BXDI. This allows the use of STLC5432 also for particu- lar cases as for optical fiber or for different pur- poses. The functions of these 6 pins are defined by the SIG bit (SIGR register) ...
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... STLC5432 XCLK (respectively Transmit Data and its clock associated). Frame and multiframe generated by the transmitter of the circuit are processed by the receiver of the circuit, without encoding and de- coding. 4.4 LOOPBACK 4 LP4 Command replaces Data in with Data out near of DIN and DOUT pins (See LP4R register). ...
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... The choice is done by means of the SA/Reset, P0 and P1 pins. 6.1 Parallel Microprocessor Interface Mode The microprocessor can read (or write) the regis- ters of the STLC5432 using the fifteen parallel In- terface pins. The use of TSO (Time Slot Zero) of DIN and DOUT digital multiplex is defined by TSOE bit of CR5 Register. – ...
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... STLC5432 R Message to write a register, addressed by the bits A0/5. The bit 7 of following byte is 1 and the seven D 0/6 bits are data to load into register. To transfer one message, 250 s are necessary. Between two messages, the bits are 1 during TS0. See fig.7 for details. 6.2.1 Reading of a register ...
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... Transmission of Sa6RR data after loading of this register. 8.3 Stand Alone Mode Interrupts are not generated. AL0, AL1 pins indicate the current state of three alarms : LOF, AIS, A bit received and DOUT pin indicates the current state of nine alarms during time-slot zero (See Par. 6.3). STLC5432 13/46 ...
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... STLC5432 Table 3: The registers and their bits. After ADD Register Reset bit 7 bit 6 (Dec.) Name (Hexa RESET ALR 1 EXT1 3 FF AMR 1 MEXT1 4 80 CAR1 1 EXT2 5 FF CAMR1 1 MEXT2 6 80 CAR2 1 PRSL 7 FF CAMR2 1 MPRSL MPRSR MMFNR MMFR 8 80 FCR1 ...
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... This bit is at ”1” when one bit out of CAR2 Register bits has been set to ”1”. 9.5 CAMR1 Complementary Alarm Mask Register MEXT2 Nu MSaRm MTSOR MER MCRCF MWER At Reset = FFH This register can be read or written. STLC5432 0 ER CRCF WER 0 15/46 ...
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... STLC5432 When a bit of this register is at ”1”, the CAR1 Register bit which has the same number is masked. The CAR1 bit which is masked do not generate an interrupt. 9.6 CAR2: Complementary Alarm Register PRSL PRSR MFNR MFR 0 After Reset = 80H SKIP SKIP. After frame recovery, this bit is at ”1” ...
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... Sa6R interrupt is generated (a new word 44 can occur each millisecond Sa5R. Thisbit is the same asSa5R in TS0RR register bit received. It’s the same bit than the AR 60 bit of ALR register (see 9.2). STLC5432 Number of erroneous Frame Alignment words received during 2 seconds ...
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... STLC5432 9.18 TS0XR: Time Slot Zero transmit Register Sa4X Sa5X Sa6X Sa7X Sa8X After Reset = 9FH Sa4X to Sa8X Bits each odd Time Slot Zero to be transmitted onto the line in accordance with CR6 and CR7 AE A bit to transmit. AX bit to be transmitted onto the line is given by the logical ” ...
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... Relevant if LTM (CR1 DELAY BETWEEN INPUT SIGNAL (LI1 OR LI2) AND OUTPUT SIGNAL (LCR) AT 8KHz AFTER SYNCHRONIZING (when SLCR = 1, LP4R Register Bit) STLC5432 SLCR = 1, LCR output signal will be syn- chronized once when MFR bit (or MFNR bit) will go to ”1”. After synchronizing, the ...
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... STLC5432 9.23 CR1: Configuration Register MERA LTM 8KCR MCR1 MCR0 SELEX SELER After Reset = 84H SELER Selection of an external signal side receiver. When SELER=1, the internal binary data signal and its clock associated are replaced by the external binary data signal and its clock associated (respectively BRDI and RCLI) ...
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... Data In are shifted on the second falling edge of the local clock (LCLK). When this bit is at ”0”, local clock frequency and data rate value have same value. Data in are shifted on the falling edge of the local clock. DEL Delayed mode. STLC5432 0 DEL DCP 21/46 ...
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... STLC5432 When DEL is at ”0”, Bit 0 of TS0 is indicated by the rising edge of Frame synchronization signal. When DEL is at ”1”, Bit 0 of TS0 is delayed; the rising edge of Frame Synchronization indicates the bit located just before Bit 0 Time Slot 0. AVT Adaptative Voltage Threshold Validation. ...
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... Sa6RR register and a Sa6R interrupt is generated. SaT = 0: each millisecond the Sa5R, Sa61R, Sa62R, Sa63R and Sa64R bits are loaded into Sa6RR register and a Sa6R interrupt is generated. STLC5432 0 For Subchannel Sa4 in Reception, the destination is: TS0RR Register receives Bit Sa4R and DOUT pin delivers Bit Sa4R ...
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... STLC5432 Transmitter side: SaT fixs the number of consencutive transmissions of Sa61 to Sa64 bits onto the line before resetting WT (Sa6XR register). See definition of WT bit in chapter 9.19 OSCD Oscillator Disabled OSCD = 1, The clock pulse applied to XTAL1 input pin comes from an external generator. The internal oscillator is disabled to reduce power consumption ...
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... Register); the associated counter indicates the number of faults received. ATS2 GTS1 GTS0 Time Slot(s) selected to receive PRBS All the Time Slots except TS0 All the Time Slots including TS0 Not use TS1 TS2 TS30 TS31 STLC5432 PRBS 25/46 ...
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... STLC5432 9.34 TCR3 Test Configuration Register CRCC EBC PELC PULS FASC ODTS TWI After Reset = 80H TWI TSO corrupted TWICE. If FASC=1 and TWI=1, Time Slot 0 selected by ODTS is corrupted twice only. If FASC=1 and TWI=0, Time Slot 0 selected by ODTS is corrupted three times only. ...
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... Figure 3: Connections with and without Internal Equalizer. (*) 60 Zc=120 60 100nF Zc=120 15 (*) To be inserted for the internal Equalizer Figure 4: STLC5432 Line Interface Configurations (CEPT 120 120 LO1 TX 120 15 LO2 LI1 120 60 LI2 0 33pF 32768MHz 33pF ...
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... STLC5432 Figure 5: Main Alarm Processing LINE STATE RECEIVING ALARMS ALARMS TRANSMITTED DETECTED ODD TS0 BIT 3 Ax LOS AIS 915 LOF AR WER Figure 6: DIN and DOUT During Time slot 0. SA pin: 0V Serial Interface Parallel Interface TSOE = 0 (CR5) During During Time Slot 0: Time Slot 0: Dout pin is High Z ...
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... SKIP = 0 SLC = X SLC = X Even frame ODD = 1 ODD = 0 SKIP = 1 SKIP = 0 SLC = 1 SLC = 1 Odd frame n Odd frame n ODD = 1 ODD = 1 SKIP = 0 SKIP = 1 SLC = X SLC = 0 STLC5432 Even frame ODD = 0 SKIP = 0 SLC = X Odd frame ODD = 1 SKIP = 0 SLC = 1 Even frame ODD = 0 SKIP = 0 SLC = 0 29/46 ...
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... STLC5432 Figure 7: DIN/DOUT multiplex during Time Slot 0 - Serial Microprocessor Interface Mode. BIT NUMBER ADDRESS REGISTER DATA 1 IDLE THE BITS ARE TRANSMITTED TO MULTIPLEX IN ORDER, BIT 1 FIRST TWO CONSECUTIVE WRITE CYCLES TSO 0 0 A0/5 DIN A 125 s WRITE CYCLE 250 s READ CYCLE ...
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... Figure 9: Level 1 - Level 2 Process with Parallel Interface P. 2Mb/s LEVEL 1 S2/T2 PRCD PARALLEL INTERFACE 20dB/dec 10Hz 40Hz DOUT TS0 Z TS16 DIN TS16 TS0 5451 5451 HDLC HDLC ST9 64Kb/s SIGNALLING LAP D POINT TO POINT P STLC5432 f d D94TL134 400Hz 100kHz SYSTEM TS0 TS16 Z LEVEL 2 D93TL055A 31/46 ...
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... STLC5432 Figure 10: Primary Rate Controller Device PRCD - TE mode with serial Microprocessor XTAL1 2Mb/s RECEIVER INTERFACE S2/T2 LTM=0 (Configuration Register1) Figure 11: Four STLC5432 in LT Mode MASTER CLOCK 32764KHz XTAL1 STLC5432 XTAL1 STLC5432 XTAL1 STLC5432 XTAL1 STLC5432 32/46 XTAL 32764KHz XTAL2 HCR LCR LFSR MEMORY ...
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... Figure 12: ETSI NT1 Option 2 STLC5432 33/46 ...
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... STLC5432 Figure 13: Synchronization Algorithm LOF = 1 LOSS OF FRAME DOUT DELIVERS ”ALL 1s” FRAME RESEARCH FRAME NO ALIGNMENT RECOVERY YES LOF = 0 DOUT IS VALIDATED. TIMER OUT 400ms STARTS. MULTIFRAME RESEARCH MULTI FRAME ALIGNMENT RECOVERY YES MFR = 1 FCR 1/2 COUNTER IS VALIDATED TO COUNT CRC4 BLOCKS RECEIVED ...
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... Figure 14: Three Cases of Synchronization. TYPICAL CASE LOF 500 s max MFR MFNR OLD EXISTING EQUIPMENT CASE LOF 500 s max MFR MFNR PARTICULAR CASE: SPURIOUS FAS LOF 500 s max MFR MFNR STLC5432 6ms max 400ms max 8ms min - 400ms max D93TL060B 35/46 ...
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... STLC5432 Figure 15: Pseudo Random Sequence Analyzer Algorithm. START SAV =1 PRS DURING ALL THE TIME SLOTS NO LOF = 1 SAV SEQUENCE ANALYZER VALIDATED LOF LOSS OF FRAME MFR MULTIFRAME RECOVERED MFNR MULTIFRAME NOT RECOVERED PRSR PSEUDO RANDOM SEQUENCE RECOVERED 36/46 NO YES NO MFNR + MFR YES YES PSEUDO RANDOM ...
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... Example applied to DIN pin with Data Rate at 2048Kb/s LFSX LCLK DIN BIT 254 BXDO BXDO output has 2 LCLK pulse of delay from DIN input 488ns 15 D93TL062B BIT 255 BIT 0 BIT 1 BIT 2 BIT 253 BIT 254 BIT 255 BIT 0 STLC5432 BIT 1 D96TL254 37/46 ...
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... STLC5432 Figure 17: Receiver Side Timing T1/2 RCLO (CLOCK BRDO (DATA) RCLI (CLOCK) BRDI (DATA) SIG = 488ns 61 (2048Kb/s) SIG = 15 (64Kb/s) T’ = 488ns 61 (RCLI e BRDI not used) Figure 18: HCR and LCR versus configuration bits. CLOCK RECOVERED FROM THE LINE RCLO ...
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... DOUT DIN DCP = 1 DOUBLE CLOCK PULSE T = 244ns MULTIPLEX AT 2Mb 122ns MULTIPLEX AT 4Mb 61ns MULTIPLEX AT 8Mb/s t=30.5ns tpd THCR THCR/2 TL TLCR td td THCR 8KCR TLCR 1 122ns 125 s (8MHz) 0 244ns 250 s (4KHz) BIT tpd STLC5432 TLCR D93TL064C tpdz D93TL065A 39/46 ...
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... STLC5432 Figure 20: Single Clock Delayed Mode. LCLK LFSX LFSR DOUT DIN DCP = 0 SINGLE PULSE T = 488ns MULTIPLEX AT 2Mb 244ns MULTIPLEX AT 4Mb 122ns MULTIPLEX AT 8Mb/s DEL = 0 NOT DELAYED MODE BIT n IS THE FIRST BIT OF THE FRAME (125 s) BIT 0 TIME SLOT ZERO (LIKE GCI) ...
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... CCITT 32540 A 0 20dB/DECADE SLOPE JITTER FREQUENCY (LOGARITHMIC SCALE 20Hz 3.6kHz STLC5432 IDEAL PULSE 10% 10 D93TL069A 18kHz 100kHz 41/46 ...
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... STLC5432 Multiplexed Motorola-like P bus timing. ( 5V) t WAS AAS ADDRESS AD0/7 Signal name Corresponding pin AS AS/ALE (13) DS DS/RD (21) R/W R/W/WR (26 (35) A/D0 to A/D7 AD0 ........30) Symbol Parameter t AS Pulse Width WAS t DS Pulse Width WDS t AS low to DS high ASDS t R setup ...
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... Parameter t Data to DS setup DWS t Data Hold after DS DWH t ASDS t RWS t WDS t CSS t AAH t DV READ DATA VALID t DWS WRITE DATA VALID D93TL072B STLC5432 t RWH t CSH t DF AD0/7 READ CYCLE AD0/7 WRITE CYCLE t DWN Min. Max. Unit 30 ns 110 ...
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... STLC5432 Multiplexed Intel-like P bus timing. ( 5V) READ CYCLE t WA ALE CS. ADDR WRITE CYCLE CS.WR AD0/7 READ CYCLE (Multiplexed Intel Mode) Symbol Parameter t Address Hold After ALE LA t Address to ALE Setup AL t Data Delay from Pulse Width RR t Output Float Delay ...
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... MAX. MIN. 1.60 0.15 0.002 1.45 0.053 0.45 0.012 0.20 0.004 0.75 0.018 STLC5432 inch TYP. MAX. 0.063 0.006 0.055 0.057 0.014 0.018 0.008 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.024 0.030 0.10mm .004 Seating Plane C ...
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... STLC5432 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice ...