STLC5432 ST Microelectronics, STLC5432 Datasheet - Page 18

• Manufacturer Part Number: STLC5432
• Description: 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE
• Manufacturer: ST Microelectronics

STLC5432
9.18 TS0XR: Time Slot Zero transmit Register
7
Sa4X to Sa8X Bits 4 to 8 of each odd Time Slot
AE
WT
9.19 Sa6XR: Sa6 Bits Transmit Register
7
Sa61X, Sa62X, Sa63X, Sa64X
These four bits are transmitted on subchannel
Sa6 in accordance with CR6 and CR7 Registers.
WT
9.21 SIGR: Signalling Register
7
18/46
1
1
1
WT
SHCR SIG
WT
A bit to transmit.
AX bit to be transmitted onto the line is given
by the logical ”or” of LOF (Loss of Frame),
WER (if the bit MERA is at 0, CR1 register)
and AE (see fig 5).
AX(Odd TS0 Bit3) = AE + LOF + WER NOT
MERA
Word to Transmit. This bit is read only.
First Case FILT = 1.
After TS0XR writing by microprocessor with
WT = 1, WT is resettedat ”0” afterthree
consecutive transmissions of Sa4X to
Sa8X bits onto the line.
Second Case FILT = 0.
After TSOXR writing by microprocessor with
WT = 1, WT is resettedat ”0” afterone
transmission of bits located in TS0XRregister.
Word to Transmit. This bit is read only.
First Case SaT = 1.
After Sa6XR writing by microprocessor,
WT = 1. WT is resettedat ”0” afterthree
consecutive transmissions of Sa61X to
Sa64X bits onto the line.
Second Case SaT = ”0”.
After Sa6XR writing by microprocessor,
WT = 1, WT is resetted at ”0” after one
transmission of bits located in Sa6XR
Register.
Nu
AE
Zero to be transmitted onto the line
in accordance with CR6 and CR7
Nu Sa61X Sa62X Sa63X Sa64X
After Reset = 9FH
After Reset = 8FH
After Reset = 90H
Sa4X Sa5X Sa6X Sa7X Sa8X
STS4 STS3 STS2 STS1 STS0
0
0
0
STS 0/4 Signalling Time Slot 0/4:
SIG
SHCR: Synchronization of High Clock Received.
9.22 LP4R: Loop Back 4 Register
7
LTS 0/4Loo Back time Slot 0/4:
DPIS
1
0
0
1
1
SLCR LP4
these five bits indicate which time Slot out
of 32 to transmit and to receive on BRD0 and
BXDI pins respectively, when SIG bit is at 1.
Signalling Validated.
Receiver Side :
When SIG is at ”1”, the contents of Time
Slot selected appear on the BRDO pin at
64 kb/s and its clock associated o
the RCLO pin at 64kHz.
When SIG is at ”0”, the contentsof 32 Time
slots received appear onto BRDO pin at
2 048 kb/s and clock associated onto
RCLO pin at 2 048 kHz.
transmitter side :
When SIG is at ”1”, a bit stream at 64 kb/s
on BXDI pin will be introduced into time
Slot, selected by STS0 to STS4 bits, to
the line. The bit stream on the input BXDI
pin is clocked by clock at 64KHz delivered
by BXDO pin (BXDI pin is an input and
BXDO pin is an output).
When SIG is at ”0”, the bit stream at 2 048
kb/s on BXDI pin will be introduced into 32
Time Slots to the line.
If DPIS (CR5) = 0:
SHCR = 1, DPLL receives RCLI signal
from RCLI pin.
SHCR = 0, DPLL receives the remoteclock
recovered from the line.
If DPIS (CR5) = 1:
SHCR is not taken into account.
these five bits indicate which time slot out
of the 32 is selected for the loopback.
SHCR
0
1
0
1
After Reset = 80 H
Source of the signal at the DPLL
LTS4 LTS3 LTS2 LTS1 LTS0
RCLI pin
DPI pin
DPI pin
input:
line
0