MC33910 Freescale Semiconductor, MC33910 Datasheet - Page 39

• Manufacturer Part Number: MC33910
• Description: LIN System Basis Chip
• Manufacturer: Freescale Semiconductor

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Interrupt Mask Register - IMR
respective flags within the ISR will continue to work but will
not generate interrupts to the MCU. The 5V Regulator over-
temperature prewarning interrupt and under-voltage (VSUV)
interrupts can not be masked and will always cause an
interrupt.
ISR.
HSM - High Side Interrupt Mask
the high side block.
LINM - LIN Interrupts Mask
the LIN block.
Table 28. Interrupt Sources
Analog Integrated Circuit Device Data
Freescale Semiconductor
ISR3 ISR2 ISR1 ISR0
0
0
0
0
0
0
0
This register allow to mask some of interrupt sources. The
Writing to the interrupt mask register (IMR) will return the
This write-only bit enables/disables interrupts generated in
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled
This write-only bit enables/disables interrupts generated in
1 = LIN Interrupts Enabled
0 = LIN Interrupts Disabled
Table 26. Interrupt Mask Register - $E
Condition
0
0
0
0
1
1
1
Reset
Reset
Value
Write
0
0
1
1
0
0
1
HSM
C3
1
0
1
0
1
0
1
0
(Low-voltage and VDD over-temperature)
C2
-.
1
POR
Voltage monitor interrupt
LINM
C1
1
none maskable
no interrupt
VMM
-
-
-
C0
1
Interrupt Source
Interrupt Source Register - ISR
the last interrupt or wake-up respectively. A read of the
register acknowledges the interrupt and leads IRQ pin to
high, in case there are no other pending interrupts. If there
are pending interrupts, IRQ will be driven high for 10µs and
then be driven low again.
mask register (IMR).
ISRx - Interrupt Source Register
Table
interrupt sources are handled sequentially multiplex.
VMM - Voltage Monitor Interrupt Mask
the voltage monitor block. The only maskable interrupt in the
voltage monitor block is the V
LIN interrupt (RXSHORT, TXDOM, LIN OT, LIN
This write-only bit enables/disables interrupts generated in
1 = Interrupts Enabled
0 = Interrupts Disabled
This register allows the MCU to determine the source of
This register is also returned when writing to the interrupt
These read-only bits indicate the interrupt source following
In case more than one interrupt is pending, than the
28. If no interrupt is pending than all bits are 0.
Table 27. Interrupt Source Register - $E/$F
HS interrupt (Over-temperature)
Read
L1 wake-up from Stop Mode-
Voltage monitor interrupt
OC) or LIN wake-up
Forced wake-up
(High-voltage)
no interrupt
maskable
Reserved
ISR3
S3
LOGIC COMMANDS AND REGISTERS
FUNCTIONAL DEVICE OPERATIONS
ISR2
S2
SUP
over-voltage interrupt.
ISR1
S1
ISR0
S0
Priority
highest
lowest
none
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