NCP5393 ON Semiconductor, NCP5393 Datasheet - Page 18

• Manufacturer Part Number: NCP5393
• Description: 2/3/4-Phase Controller
• Manufacturer: ON Semiconductor

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Protection Features:
Undervoltage Lockout
V
controller is monitored, and the PWM outputs and the
soft-start circuit are disabled until the input voltage exceeds
the threshold voltage of the UVLO comparator. The UVLO
comparator incorporates hysteresis to avoid chattering,
since V
initiates soft-start.
Overcurrent Shutdown
within the IC. A comparator and latch make up this function.
The inverting input of the comparator is connected to the
ILIM pin. The voltage at this pin sets the maximum output
current the converter can produce. The ROSC pin provides
a convenient and accurate reference voltage from which a
resistor divider can create the overcurrent setpoint voltage.
Although not actually disabled, tying the ILIM pin directly
to the ROSC pin sets the limit above useful levels -
effectively
comparator noninverting input is the summed current
information from the VDRP minus offset voltage. The
overcurrent latch is set when the current information
exceeds the voltage at the ILIM pin. The outputs are pulled
low, and the soft-start is pulled low. The outputs will remain
disabled until the V
the ENABLE input is brought low and then high.
Output Overvoltage and Undervoltage Protection and
Power Good Monitor
operation, if the output voltage is 250 mV over the DAC
CCP
An undervoltage lockout (UVLO) senses the V
A programmable overcurrent function is incorporated
An output voltage monitor is incorporated. During normal
input. During powerup, the input voltage to the
CC
is likely to decrease as soon as the converter
disabling
CC
voltage is removed and re-applied, or
overcurrent
Figure 12. Soft-Start Sequence to Vcore = 1.3 V
shutdown.
CC
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The
and
NCP5393
18
voltage, the PWRGOOD goes low, the DRVON signal
remains high, the PWM outputs are set low. The outputs will
remain disabled until the V
reapplied. Every time the OV is triggered it will increment
the OV counter. If the counter reaches a count of 16 then the
OV condition will latch into a permanent OV state. It will
require POR or disable/enable to restart. Prior to latching if
the OV condition goes away then normal operation will
resume. An OV decrement counter is also incorporated. It
consists of a free-running clock which runs at 8x the PWM
frequency. So essentially every 4096 PWM cycles the OV
counter will decrement. For example, for a max PWM
frequency of 1 MHz, the counter decrements roughly every
4 ms and for a PWM frequency of 400 kHz, it would be
about every 10 ms. During normal operation, if the output
voltage falls more than 350_mV below the DAC setting, the
PWRGOOD pin will be set low until the output voltage
rises.
Soft-Start
fixed rate of 2 ms (0.8 mV/uS), and then reads the VID pins
to determine the DAC setting. Then ramps V
DAC setting at the Dynamic VID slew rate of up to
3.25 mV/mS. In SVI mode, SoftStart Time is intended as the
time required by the device to set the output voltages to the
Pre-PWROK Metal VID. In PVI mode, VID[0:5] or V_FIX
VID in V_FIX mode are the set output voltages. Typical soft
start sequence timing in SVI mode is given in Figure 12.
The NCP5393 simply ramps V
CC
voltage is removed and
core
to boot voltage at a
core
to the final