NCP5393 ON Semiconductor, NCP5393 Datasheet - Page 14

• Manufacturer Part Number: NCP5393
• Description: 2/3/4-Phase Controller
• Manufacturer: ON Semiconductor

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Differential Current Sense Amplifiers and Summing
Amplifier
output current of each phase. The inputs of each current
sense amplifier must be connected across the current sensing
element of the phase controlled by the corresponding gate
output (G1, G2, G3, or G4). If a phase is unused, the
differential inputs to that phase's current sense amplifier
must be shorted together and connected to the GND.
a summing amplifier to have a summed-up output. The
outputs of current sense amplifiers control three functions.
First, the summing current signal of all phases will go
through DROOP amplifier and join the voltage feedback
loop for output voltage positioning. Second, the output
signal from DROOP amplifier also goes to ILIM amplifier
to monitor the output current limit. Finally, the individual
phase current contributes to the current balance of all phases
by offsetting their ramp signals of PWM comparators.
Oscillator and Triangle Wave Generator
dual-Oscillator: one section is used for the CORE and it is
a multiphase programmable oscillator managing equal
phase-shift among all phases and the other section is used
for the NB section. The oscillator's frequency is
programmed by the resistance connected from the ROSC
pin to ground. The user will usually form this resistance
from two resistors in order to create a voltage divider that
uses the ROSC output voltage as the reference for creating
the current limit setpoint voltage. The oscillator frequency
range is 100_kHz per phase to 1.0_MHz per phase. The
Four differential amplifiers are provided to sense the
The current signals sensed from inductor DCR are fed into
The controller embeds a programmable precision
Figure 9. Power Up Sequences Before and After Soft Start in PVI Mode
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NCP5393
14
oscillator generates up to 4 symmetrical triangle waveforms
with amplitude between 1.3_V and 2.3_V. The triangle
waves have a phase delay between them such that for 2-, 3-
and 4-phase operation the PWM outputs are separated by
180, 120, and 90 angular degrees, respectively.
VDDNB oscillator does not accidentally lock to the VDD
oscillator, the VDDNB oscillator will free-run at a
frequency which is nominally 1.25 ratio of f
CPU Support
and configure itself accordingly. At system Start-up, on the
rising-edge of the EN signal, the device monitors the status
of VID1 and switches in PVI mode (VID1 = 1) or SVI mode
(VID1 = 0). When in PVI mode, NCP5393 uses the
information available on the VID[0:5] bus to address the
CORE Section output voltage. NB Section is kept in HiZ
mode. When in SVI mode, NCP5393 discards the
information available on VID0, VID4 and VID5 and uses
VID2 and VID3 for SVC and SVD respectively.
PVI - Parallel Interface
CORE Section reference. According to the selected code,
the device sets the CORE Section reference and regulates its
output voltage. NB Section is kept in HiZ; no activity is
performed on this section. furthermore, PWROK
information is ignored as well since the signal is propietary
of the SVI protocol. Start-up sequences before soft start and
after soft start are given in Figure 9. Voltage identifications
for the 6Bit AMD mode is given in Table 1.
When the NB phase is enabled, in order to ensure that the
NCP5393 is able to detect the CPU it is going to supply
PVI is a 6-bit-wide parallel interface used to address the
VDD
.