NCP5393 ON Semiconductor, NCP5393 Datasheet - Page 15

• Manufacturer Part Number: NCP5393
• Description: 2/3/4-Phase Controller
• Manufacturer: ON Semiconductor

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SVI - Serial Interface
single master (AMD processor) to one NCP5393. The
master initiates and terminates SVI transactions and drives
the clock, SVC, and the data SVD, during a transaction. The
slave receives the SVI transactions and acts accordingly.
SVI wire protocol is based on fast-mode I
communications are given in Figure 10.
start-up. The device returns a PWRGOOD signal if the
output voltages are in regulation. The VID codes for SVI are
given in Table 2.
given in Figure 11.
Table 1. SIX-BIT PARALLEL VID CODES in PVI Modes
SVI is a two wire, Clock and Data, bus that connects a
SVI interface also considers EN and PWROK signals for
The start-up sequences before and after soft start are
SVID[5:0]
00_0000
00_0001
00_0010
00_0011
00_0100
00_0101
00_0110
00_1000
00_1001
00_1010
00_1011
00_1100
00_1101
10_0111
00_1110
00_1111
V
1.5500
1.5250
1.5000
1.4750
1.4500
1.4250
1.4000
1.3750
1.3500
1.3250
1.3000
1.2750
1.2500
1.2250
1.2000
1.1750
OUT
(V)
SVID[5:0]
01_0000
01_0001
01_0010
01_0100
01_0101
01_1000
01_1001
01_1010
01_0011
01_0110
01_0111
01_1011
01_1100
10_1101
01_1110
01_1111
2
C. The SVI
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V
1.1500
1.1250
1.1000
1.0750
1.0500
1.0250
1.0000
0.9750
0.9500
0.9250
0.9000
0.8750
0.8500
0.8250
0.8000
0.7750
OUT
NCP5393
(V)
15
SVID[5:0]
10_0000
10_0001
10_0010
10_0011
10_0100
10_0101
10_0110
10_1000
10_1001
10_1010
10_1011
10_1100
10_1101
10_0111
10_1110
10_1111
Figure 10. SVI Communication - Send Byte
V
0.7625
0.7500
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6325
0.6250
0.6125
0.6000
0.5875
0.5750
OUT
(V)
SVID[5:0]
11_0000
11_0001
11_0010
11_0011
11_0100
11_0101
11_0110
11_0111
11_1000
11_1001
11_1010
11_1011
11_1100
11_1101
11_1110
11_1111
V
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875
0.4750
0.4625
0.4500
0.4375
0.4250
0.4125
0.4000
0.3875
0.3750
OUT
(V)