NCP5318 ON Semiconductor, NCP5318 Datasheet - Page 24

• Manufacturer Part Number: NCP5318
• Description: Two/Three/Four-Phase Buck CPU Controller
• Manufacturer: ON Semiconductor

MOSFET:
I RMS,CNTL + (D
inductor of value L
the applied gate drive voltage. Q
threshold portion of the gate−to−source charge plus the
gate−to−drain charge. This may be specified in the data sheet
or approximated from the gate−charge curve as shown in the
Figure 25.
dissipation can be approximated from:
where:
(I Lo,MAX 2 * I Lo,MAX
P D,SYNCH + (I RMS,SYNCH 2
I
I
I
I
D is the duty cycle of the converter:
DI
R
For the lower or synchronous MOSFET, the power
RMS,CNTL
Lo,MAX
Lo,MIN
O,MAX
DS(on)
Lo
) (Vf diode
I
V
f
Q
MOSFET.
Q
output charges specified in the data sheets, or
estimated from integrating C
V
Vf
intrinsic diode at the converter output current.
t
and lower gate drivers to prevent cross conduction.
This time is usually specified in the data sheet for the
driver IC.
is the peak−to−peak ripple current in the output
nonoverlap
g
sw
IN
RR
oss
IN
DI Lo + (V IN * V OUT )
is the output current from the gate driver IC.
diode
is the maximum converter output current.
is the minimum output inductor current:
is the ON resistance of the high side MOSFET at
is the maximum output inductor current:
is the switching frequency of the converter.
.
is the input voltage to the converter.
is the sum of the high and low side MOSFET
is the reverse recovery charge of the lower
is the RMS value of the current in the control
I Lo,MAX +
I Lo,MIN +
is the forward voltage of the MOSFET’s
Q switch + Q gs2 ) Q gd
is the non−overlap time between the upper
o
:
I O,MAX
D + V OUT
I O,MAX
I Lo,MIN )
I O,MAX
V IN
f
f
t nonoverlap
* DI Lo
switch
) DI Lo
(Lo
R DS(on) )
OSS
I Lo,MIN 2
2
2
from zero volts to
D
is the post gate
3
f SW )
f SW )
)) 1 2
(eq. 21)
(eq. 22)
(eq. 23)
(eq. 24)
(eq. 25)
(eq. 26)
(eq. 27)
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24
when the MOSFET is ON and the second term represents the
diode losses that occur during the gate non−overlap time.
control MOSFET with the exception of:
I RMS,SYNCH + ((1 * D)
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient operating temperature.
where:
copper clad circuit boards will have approximate thermal
resistances (q
(I Lo,MAX 2 ) I Lo,MAX
V
The first term represents the conduction or I
All terms were defined in the previous discussion for the
When the MOSFET power dissipations are known, the
For TO−220 and TO−263 packages, standard FR−4
GS_TH
Figure 25. MOSFET Switching Characteristics
Q
Pad Size (in
GS1
q
q
MOSFET;
q
the heatsink assuming direct mounting of the
MOSFET if no thermal “pad” is used;
T
temperature;
T
T
JC
SA
A
J
is the total thermal impedance (q
0.50/323
0.75/484
1.00/645
1.50/968
is the worst case ambient operating temperature.
is the specified maximum allowed junction
is the junction−to−case thermal impedance of the
is the sink−to−ambient thermal impedance of
Q
SA
GS2
) as shown below:
2
/mm
q T t (T J * T A ) P D
2
)
Q
GD
I Lo,MIN )
I
Single−Sided 1 oz. Copper
D
I Lo,MIN 2
60−65°C/W
55−60°C/W
50−55°C/W
45−50°C/W
V
3
DRAIN
JC
V
GATE
+ q
)) 1 2
2
SA
R losses
(eq. 28)
(eq. 29)
);