NCP5318 ON Semiconductor, NCP5318 Datasheet - Page 15

• Manufacturer Part Number: NCP5318
• Description: Two/Three/Four-Phase Buck CPU Controller
• Manufacturer: ON Semiconductor

CSxP) that accepts inductor current information for each
phase as shown in Figure 17. The triangular inductor current
is measured across R
with the channel startup offset, the internal ramp and the
output voltage. The internal ramp provides greater design
flexibility by allowing smaller external (current) ramps,
lower minimum pulse widths, higher frequency operation
and PWM duty cycles above 50% without external slope
compensation.
output of any phase) transitions to a high voltage at the start
of the oscillator cycle for that phase, commanding a power
stage to switch on. Inductor current in that power stage then
ramps up until the combination of startup offset voltage, its
current sense signal, its internal ramp and the output voltage
ripple exceed the compensated feedback signal at the other
PWM comparator input. This brings GATEx low, which
commands that power stage off. While GATEx is high, the
Enhanced V
variations, but once GATEx is low, that phase cannot
respond until the next start of its oscillator cycle. Therefore,
the NCP5318 will take, at most, the off−time of the oscillator
to respond to disturbances. With multiple phases, the time to
respond to disturbances is significantly reduced due to the
increased likelihood of a GATEx being high, and closer
average proximity of oscillator starts, however the
magnitude of that response (for equivalent total inductance)
is equivalently reduced.
terminate the PWM cycle earlier, providing negative
feedback. Current sharing is accomplished by referencing
the PWM comparators of all phases to the same Error
Amplifier signal (COMP pin).
Error Amplifier Output (COMP) Voltage No Load Bias
Point
comparator’s non−inverting input is the sum of the channel
startup offset, output voltage, and the inductor current and
internal ramps corresponding to that phase. When the
average output current is zero, the Error Amplifier output at
the COMP pin will be:
Ramp Amplitude” = 100 mV at a 50% duty cycle)
corresponding to the steady state duty cycle, Ext_Ramp is the
peak−to−peak external steady−state current ramp appearing
across CSxP to CSxN, G
gain (“Current Sense Amp to PWM Gain” = 3.0 V/V).
The NCP5318 provides a differential input (CSxN and
When the controller is enabled, GATEx output (GATE
Turn on of a phase with higher inductor current will
As shown in Figure 17, the voltage present at each PWM
Int_Ramp is the fraction of the internal ramp (“Artificial
V COMP + V OUT ) Channel_Startup_Offset
2
control circuit will respond to line and load
) Int_Ramp ) G CSA
S
and amplified before being summed
CSA
is the current sense amplifier
Ext_Ramp
2
http://onsemi.com
15
sensing” is used as in Figure 19, the magnitude of Ext_Ramp
is:
where D is duty cycle expressed as a fraction.
the input voltage V
1.480/12.0 or 12.3%. Int_Ramp will be 100 mV/50% x
12.3% = 25 mV. Realistic values for R
2.5 kW, 0.1 mF and 350 kHz. Using these and the previously
mentioned formula, Ext_Ramp will be 14.8 mV.
Error Amplifier Output (COMP) Voltage Bias Point
Change with Load
in order to maintain the output voltage constant when load
current changes. The required change at the COMP pin
depends partially on the scaling of the current feedback
signal as follows:
N is the number of phases.
efficiency causes the change in input power to exceed the
change in output power, and the duty cycle becomes:
DD + D * D +
nearly (1− Efficiency) / Efficiency, thereby changing the
amplitude of the external ramp by this amount. The
complete change required at the COMP pin will therefore
be:
DV + R S
Ext_Ramp + D
When the technique known as “lossless inductor current
For example, if V
In a closed loop configuration, the COMP pin may move
where R
Also, when load current changes, nonideal conversion
and
Peak to peak ripple current therefore also changes by
(Int_Ramp ) G CSA
V COMP + 1.480 V ) 0.60 V ) 25 mV
S
is the current sense resistance in each phase and
G CSA
DV + R S
+
Efficiency
+ 2.127 Vdc.
D
(V IN * V OUT ) (R CSx
OUT
IN
) 3.0 V
D +
D
2
is 12.0 V, the duty cycle (D) will be
(1 * Efficiency)
DI OUT
Efficiency
at zero load is set to 1.480 volts and
V
N
Efficiency
G CSA
*
Ext_Ramp)
(D
)
D
14.8 mV
Efficiency
2
Efficiency)
DI OUT
CSx
N
, C
CSx
(1 * Efficiency)
C CSx @ f SW )
Efficiency
and f
SW
are