NCP5318 ON Semiconductor, NCP5318 Datasheet - Page 18

• Manufacturer Part Number: NCP5318
• Description: Two/Three/Four-Phase Buck CPU Controller
• Manufacturer: ON Semiconductor

Transient Response and Adaptive Voltage Positioning
filter is frequently sized larger than ripple currents require in
order to reduce voltage excursions during load transients. In
addition, adaptive voltage positioning can reduce
peak−peak output voltage deviations due to load transients
and allow use of a smaller output filter. Adaptive voltage
positioning sets output voltage higher than nominal at light
loads, and output voltage is allowed limited sag when the
load current is applied. Upon removal of the load, output
voltage returns no higher than the original level, allowing
one output transient peak to be canceled over a load
application and release cycle.
series with the output can provide fast, accurate adaptive
positioning. However, at high currents, the loss in a dropping
resistor becomes excessive. For example, a 50 A converter
with a 1.0 mW resistor would provide a 50 mV change in
output voltage between no load and full load and would
dissipate 2.5 W. Lossless Adaptive Voltage Positioning
(AVP) is an alternative to using a droop resistor. Figure 20
shows how AVP works. The waveform labeled “normal”
shows a converter without AVP.
On the left, the output voltage sags when the output current
is stepped up and later overshoots when current is stepped
back down. With fast (ideal) AVP, the peak−to−peak
excursions are cut in half. In the slow AVP waveform, the
output voltage is not repositioned quickly enough after
current is stepped up and the upper limit is exceeded. The
controller can be configured to adjust the output voltage
based on the output current of the converter as shown in the
application diagram in Figure 1. The no−load positioning is
set internally to VID − 19 mV, reducing the potential error
due to resistor and bias current mismatches. In order to
realize the AVP function, a resistor divider network is
connected between V
conditions, the V
pin. As the output current increases, the V
increases proportionally. This drives the V
causing V
resistor divider network. The response during the first few
microseconds of a load transient is controlled primarily by
power stage output impedance, and by the ESR and ESL of
For applications with fast transient currents, the output
For low current applications, a simple dropping resistor in
Figure 20. Adaptive Voltage Positioning
OUT
Normal
Slow
Fast
Limits
to “droop” according to a loadline set by the
Adaptive Positioning
Adaptive Positioning
DRP
FB
pin is at the same voltage as the V
, V
DRP
and V
OUT
FB
. During no−load
DRP
voltage higher,
pin voltage
http://onsemi.com
FB
18
the output filter. The transition between fast and slow
positioning is controlled by the total ramp size and the error
amp compensation. If the ramp size is too large or the error
amp too slow, there will be a long transition to the final
voltage after a transient. This will be most apparent with low
capacitance output filters.
Overvoltage Protection
control topology is provided by operation of the
synchronous rectifiers. The control loop responds to an
overvoltage condition within 40 ns, causing the GATEx
output to shut off. The (external) MOSFET driver should
react normally to turn off the top MOSFET and turn on the
bottom MOSFET. This acts quickly to discharge the output
voltage and prevent damage to the load. The regulator will
remain in this state until the fault latch is reset by cycling
power at the V
200 mV above the VID voltage, the converter will latch off.
soon as the V
part. The OVP circuit is then always active, regardless of
operating status.
Power Good
(PWRGD) signal must be asserted when the output voltage
is within a window defined by the VID code, as shown in
Figure 21. The PWRLS pin is provided to allow the
PWRGD comparators to accurately sense the output
voltage. The effect of the PWRGD lower threshold can be
modified using a resistor divider from the output to PWRLS
to ground, as shown in Figure 22.
PWRGD
HIGH
Overvoltage Protection (OVP) in the Enhanced V
The OVP circuit begins monitoring the output voltage as
According to the latest specifications, the Power Good
LOW
Figure 22. Adjusting the PWRGD Threshold
Figure 21. PWRGD Assertion Window
PWRGD
low
CC
CC
V
OUT
voltage exceeds the UVLO threshold of the
Ç Ç Ç
Ç Ç Ç
Ç Ç Ç
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Ç Ç Ç É É É É
É É É
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pin. If the voltage at the V
−2.6
%
V
LOWER
R1
R2
+2.6%
PWRGD
high
PWRLS
Ç Ç Ç Ç
Ç Ç Ç Ç
Ç Ç Ç Ç
Ç Ç Ç Ç
É É É É
É É É É
VID + 80 mV
−5.0
%
FFB
+5.0%
pin exceeds
PWRGD
low
V
OUT
2