SiP41105 Vishay Siliconix, SiP41105 Datasheet
SiP41105
Related parts for SiP41105
SiP41105 Summary of contents
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... D Multi-Phase DC/DC Conversion D High Current Synchronous Buck Converters D High Frequency Synchronous Buck Converters D Asynchronous-to-Synchronous Adaptations D Mobile Computer DC/DC Converters D Desktop Computer DC/DC Converters The SiP41105 is available in a 16-Pin TSSOP PowerPAKr package and is specified to operate over the industrial temperature range of − _C BOOT ...
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... SiP41105 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS (ALL VOLTAGES REFERENCED TO GND = PWM, SD DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DD SYNC LX, BOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... See Timing Waveforms See Timing Waveforms Temperature Rising Temperature Falling with external capacitor. 50% 50% 90% 10% fH 90% 10 d(off)L t d(on SiP41105 www.DataSheet4U.com Vishay Siliconix Limits = Min Typ Max 420 4 ...
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... SYNC OUT ORDERING INFORMATION Temperature Range −40 to 85_C Eval Kit Temperature Range SiP41105DB −40 to 85_C Function , the driver for the synchronus MOSFET L www.DataSheet4U.com TRUTH TABLE SD EN OUT OUT SYNC ...
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... After the voltage on OUT drops below 1 V the high-side driver is enabled and OUT go high after an internal propagation delay does not drop below 1 V within 400 ns after OUT high until the next PWM transition. SiP41105 www.DataSheet4U.com Vishay Siliconix BOOT OUT ...
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... SiP41105 Vishay Siliconix Delay The addition of a capacitor between DELAY and GND will increase the propagation delay time for OUT Delay capacitance may be added to prevent shoot through current in the low-side MOSFET due to the finite time between OUT going low and the continuing conduction of the low-side L MOSFET ...
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... V/div Delay EN SYNC 5 V/div HS Gate 5 V/div LS Gate 5 V/div For related documents such as package/tape drawings, part marking, and reliability data, see SiP41105 www.DataSheet4U.com Vishay Siliconix PWM Signal vs. LX (Falling) Figure 3. 50 ns/div PWM Signal vs. HS Gate Figure 5. and LS Gate (Falling) 50 ns/div www.vishay.com ...