SI3211 ETC, SI3211 Datasheet - Page 113

• Manufacturer Part Number: SI3211
• Description: PROSLIC PROGRAMMABLE CMOS SLIC/CODEC WITH RINGING/BATTERY VOLTAGE GENERATION
• Manufacturer: ETC

Addr.
FSK Control
For detailed instructions on FSK signal generation, refer to “Application Note 32: FSK Generation” (AN32). These
registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108,
bit 6) and REL = 1 (direct Register 32, bit 6).
Addr. D15
32
33
34
35
36
37
38
39
40
41
42
43
100
101
102
103
104
99
Power Alarm Threshold for Transistors Q1 and Q2.
Power Alarm Threshold for Transistors Q3 and Q4.
Power Alarm Threshold for Transistors Q5 and Q6.
Loop Closure Filter Coefficient.
Ring Trip Filter Coefficient.
Thermal Low Pass Filter Pole for Transistors Q1 and Q2.
Thermal Low Pass Filter Pole for Transistors Q3 and Q4.
Thermal Low Pass Filter Pole for Transistors Q5 and Q6.
Common Mode Bias Adjust During Ringing.
Recommended value of 6 decimal.
DC-DC Converter V
This register sets the overhead voltage, V
When the VOV bit = 0 (direct Register 66, bit 4), V
(VMIND = 0 to 6h). When the VOV bit = 1, V
(VMIND = 0 to 9h).
Reserved.
Loop Closure Threshold—Lower Bound.
This register defines the lower threshold for loop closure hysteresis, which is enabled in
bit 0 of direct Register 108. The range is 0–80 mA in 1.27 mA steps.
D14
Table 42. SLIC Control Indirect Registers Description (Continued)
D13
Table 43. FSK Control Indirect Registers Summary
OV
D12
Voltage (Si3210 only).
D11
D10
Description
Preliminary Rev. 1.11
OV
D9
, to be supplied by the dc-dc converter.
OV
FSK0X[15:0]
FSK1X[15:0]
FSK01[15:0]
FSK10[15:0]
should be set between 0 and 13.5 V
FSK0[15:0]
FSK1[15:0]
D8
OV
should be set between 0 and 9 V
D7
Si3210/Si3211/Si3212
D6
D5
D4
D3
D2
Reference Page
D1
24
24
24
26
36
24
24
24
33
27
26
D0
113