IDT70T3589 Integrated Device Technology, IDT70T3589 Datasheet - Page 17

• Manufacturer Part Number: IDT70T3589
• Description: 64k X 36 Sync, 3.3v/2.5v Dual-port Ram, Interleaved I/o S
• Manufacturer: Integrated Device Technology

Timing Waveform of Flow-Through Read-to-Write-to-Read ( OE = V
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE
3. Addresses do not have to be accessed sequentially since ADS = V
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
ADDRESS
reference use only.
DATA
ADDRESS
DATA
0
, BEn, and ADS = V
DATA
DATA
CLK
R/
CE
CE
BEn
OUT
OE
W
IN
R/
CLK
CE
CE
BEn
0
1
OUT
(3)
W
IN
0
1
(3)
(1)
t
t
t
(1)
SB
t
SW
SC
SA
t
t
IL
t
t
SB
SW
An
SC
SA
; CE
t
t
t
t
An
HW
HC
HB
HA
t
t
1
CH1
t
t
CD1
t
t
, CNTEN, and REPEAT = V
HW
HC
HA
HB
t
t
CH1
CD1
t
CYC1
READ
t
CYC1
t
CL1
READ
Qn
t
CL1
An +1
Qn
An +1
t
DC
t
DC
t
OHZ
t
CD1
IH
.
t
t
SW
SD
An + 2
Dn + 2
Qn + 1
IL
An + 2
t
t
HD
constantly loads the address on the rising edge of the CLK; numbers are for
HW
6.42
17
NOP
t
CKHZ
(5)
WRITE
An + 3
Dn + 3
t
t
SW
SD
Dn + 2
An + 2
t
t
HW
HD
WRITE
Industrial and Commercial Temperature Ranges
An + 4
t
An + 3
CKLZ
t
OE
t
CD1
t
CD1
t
CKLZ
READ
Qn + 4
READ
An + 5
Qn + 3
An + 4
t
DC
t
t
DC
CD1
t
CD1
5666 drw 14
APRIL 10, 2006
5666 drw 13
IL
)
(2)
(2)