SC28L92 Philips Semiconductors, SC28L92 Datasheet - Page 22

• Manufacturer Part Number: SC28L92
• Description: 3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter DUART
• Manufacturer: Philips Semiconductors

Philips Semiconductors
CTPL
ACR
IPCR
IPR
SOPR – SET THE OUTPUT PORT BITS (OPR)
ROPR – RESET OUTPUT PORT BITS (OPR)
OPCR OUTPUT PORT CONFIGURATION REGISTER (NOTE OP1 AND OP0 ARE THE RTSN OUTPUT AND
ARE CONTROLLED BY THE MR REGISTER)
REGISTER DESCRIPTIONS Mode Registers
MR0A Mode Register 0. MR0 is accessed by setting the MR pointer to 0 via the command register command B.
MR0[7]—This bit controls the receiver watch dog timer. 0 = disable,
1 = enable. When enabled, the watch dog timer will generate a
receiver interrupt if the receiver FIFO has not been accessed within
64 bit times of the receiver 1X clock. This is used to alert the control
processor that data is in the RxFIFO that has not been read. This
situation may occur when the byte count of the last part of a
message is not large enough to generate an interrupt.
MR0[6]—Bit 2 of receiver FIFO interrupt level. This bit along with Bit
6 of MR1 sets the fill level of the FIFO that generates the receiver
interrupt.
MR0[6] MR1[6] Note that this control is split between MR0 and
MR1. This is for backward compatibility to the SC2692 and
SCN2681.
Table 3. Receiver FIFO interrupt fill level
2000 Jan 21
Configure OP7
Baud Group
3.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
Reset OP 7
Delta IP3
State of IP
Set OP 7
MR0[6] MR1[6]
MR0A/
Bit 7
–
MR0B
Bit 7
Bit 7
Addr
0x00
0x08
Bit 7
Bit 7
–
–
Bit 7
–
INPUT PORT REGISTER
AUXILIARY CONTROL REGISTER AND CHANGE OF STATE CONTROL
INPUT PORT CHANGE REGISTER
00
COUNTER TIMER PRESET REGISTER, LOWER
(MR0(3) = 0 (8 bytes)
Counter Timer mode and clock select
WATCHDOG
Delta IP2
State of IP 6
0 = Disable
1 = Enable
Reset OP 6
Set OP 6
Bit 6
Configure OP6
Bit 7
BIT 6
Bit 6
BIT 6
Rx
1 or more bytes in FIFO (Rx RDY)
BIT 6
Bit 6:4
Interrupt Condition
See Tables in
RxINT BIT 2
Delta IP1
State of IP 5
description
Reset OP 5
Bit 5
Set OP 5
BIT 6
MR0
Bit 5
BIT 5
BIT 5
Configure OP5
BIT 5
8 LSB of the BRG Timer divisor.
TxINT (1:0)
See Table 4
Delta IP0
State of IP 4
BITS 5:4
Reset OP 4
Bit 4
Set OP 4
Bit 4
BIT 4
BIT 4
Enable IP3
Bit 3
Bits 7:0
Configure OP4
22
1 = 16 byte FIFO
State of IP3
0 = 8 byte FIFO
State of IP 3
FIFO SIZE
Table 3a. Receiver FIFO interrupt fill
Reset OP 3
BIT 4
Bit 3
Set OP 3
Bit 3
BIT 3
BIT 3
BIT 3
MR0[6] MR1[6]
Enable IP2
01
10
00
01
10
11
11
Bit 2
level(MR0(3)=1 (16 bytes)
State of IP2
Configure OP3
State of IP 2
Reset OP 2
Set OP 2
EXTENDED II
BAUD RATE
1 = Extend II
Bit 2
0 = Normal
Bit 2
BIT 2
BIT 2
BIT 2
BIT(3:2)
1 or more bytes in FIFO (Rx RDY)
Enable IP1
16 bytes in FIFO (Rx FULL)
Bit 1
State of IP1
8 bytes in FIFO (Rx FULL)
12 or more bytes in FIFO
3 or more bytes in FIFO
6 or more bytes in FIFO
8 or more bytes in FIFO
Set OP 1
State of IP1
Reset OP 1
Interrupt Condition
Bit 1
TEST 2
Set to 0
BIT 1
Bit 1
BIT 1
BIT 1
Configure OP2
Product specification
SC28L92
EXTENDED 1
Enable IP0
BIT(1:0)
BAUD RATE
State of IP0
0 = Normal
1 = Extend
State of IP 0
Set OP 0
Reset OP 0
Bit 0
BIT 0
Bit 0
Bit 0
BIT 0
BIT 0