SC28L92 Philips Semiconductors, SC28L92 Datasheet - Page 13

• Manufacturer Part Number: SC28L92
• Description: 3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter DUART
• Manufacturer: Philips Semiconductors

1. Parameters are valid over specified temperature and voltage range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of
3. Test conditions for outputs: CL = 125 pF, except open drain outputs. Test conditions for open drain outputs: C
4. Typical values are the average values at +25 C and 5V.
5. Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the “strobing” input. CEN and RDN (also CEN and
6. Guaranteed by characterization of sample units.
7. If CEN is used as the “strobing” input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
8. Minimum frequencies are not tested but are guaranteed by design.
9. Clocks for 1X mode should maintain a 60/40 duty cycle or better.
10. Minimum DACKN time is t
Philips Semiconductors
NOTES:
NOTES:
2000 Jan 21
Receiver Timing, external clock (See Figure 13)
68000 or Motorola bus timing (See Figures 6, 7, 8)
SYMBOL
SYMBOL
3.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8*V
2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.
constant current source = 2.6mA.
WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.
be negated for t
while in the 68XXX mode. It is not necessary to wait for DACKN to insure the proper operation of the SC28C92. In all cases the data will be
written to the SC28L92 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the
bus cycle. DACKN low or CEN high completes the write cycle.
Bus cycle times:
t
t
t
t
t
*RXH
t
*RXS
DCW
DCR
CSC
DAT
(ns)
T
dd
(80XXX mode): t
(68XXX mode) = t
60
55
50
45
40
35
30
25
20
15
10
5
0
RxD data setup time to RxC high
RxD data hold time from RxC high
DACKN Low (read cycle) from X1 High
DACKN Low (write cycle) from X1 High
DACKN High impedance from CEN or IACKN High
CEN or IACKN setup time to X1 High for minimum DACKN cycle
0
RWD
12 pF
to guarantee that any status register changes are valid.
DD
20
CSC
+ t
DCR
RWD
30 pF
+ t
= t
DAT
40
= 70ns @ 5V, 40ns @ 3.3V + rise and fall time of control signals
Figure 3. Port Timing vs. Capacitive Loading at typical conditions
DSC
+ 1 cycle of the X1 clock @ 5V + rise and fall time of control signals
+ t
DCR
60
+ two positive edges of the X1 clock. For faster bus cycles, the 80XXX bus timing may be used
PARAMETER
PARAMETER
80
10
10
100 pF
100
CC
120
13
pF
125 pF
. All time measurements are referenced at input voltages of 0.8 V and
140
160
180
Min
50
50
10
200
L
LIMITS
Typ
= 125 pF,
40
40
15
15
SD00684
220
8
8
230 pF
4
Max
240
Product specification
20
20
10
SC28L92
V
5.0V @ +25 C
CC
= 3.3V @ +25 C
UNIT
UNIT
ns
ns
ns
ns
ns
ns