ST16C552 Exar Corporation, ST16C552 Datasheet - Page 22

• Manufacturer Part Number: ST16C552
• Description: DUAL UART WITH 16-BYTE FIFO AND PARALLEL PRINTER PORT
• Manufacturer: Exar Corporation

ST16C552/552A
LCR BIT-6:
When enabled the Break control bit causes a break
condition to be transmitted (the TX output is forced to
a logic 0 state). This condition exists until disabled by
setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition. (normal default
condition)
Logic 1 = Forces the transmitter output (TX) to a logic
0 for alerting the remote receiver to a line break
condition.
LCR BIT-7:
The internal baud rate counter latch and Enhance
Feature mode enable.
Logic 0 = Divisor latch disabled. (normal default
condition)
Logic 1 = Divisor latch and enhanced feature register
enabled.
Modem Control Register (MCR)
This register controls the interface with the modem or
a peripheral device.
MCR BIT-0:
Logic 0 = Force -DTR output to a logic 1. (normal
default condition)
Logic 1 = Force -DTR output to a logic 0.
MCR BIT-1:
Logic 0 = Force -RTS output to a logic 1. (normal
default condition)
Logic 1 = Force -RTS output to a logic 0.
MCR BIT-2:
This bit is used in the Loop-back mode only. In the
Bit-5
LCR
Rev. 3.40
X
0
0
1
1
Bit-4
LCR
X
0
1
0
1
Bit-3
LCR
0
1
1
1
1
Parity selection
No parity
Odd parity
Even parity
Force parity odd parity
Forced even parity
22
loop-back mode this bit is use to write the state of the
modem -RI interface signal.
MCR BIT-3: (Used to control the modem -CD signal
in the loop-back mode.)
Logic 0 = Forces INT (A-B) outputs to the three state
mode. (normal default condition) In the Loop-back
mode, sets -CD internally to a logic 1.
Logic 1 = Forces the INT (A-B) outputs to the active
mode. In the Loop-back mode, sets -CD internally to
a logic 0.
MCR BIT-4:
Logic 0 = Disable loop-back mode. (normal default
condition)
Logic 1 = Enable local loop-back mode (diagnostics).
MCR BIT 5-6:
Not Used - initialized to a logic 0.
MCR BIT-7:
Logic 0 = Disable power down mode. (normal, default
condition, 552 only)
Logic 1 = Enable power down mode (IER bit-5 must
also be a logic 1 before power down will be activated).
Line Status Register (LSR)
This register provides the status of data transfers
between. the 552/552A and the CPU.
LSR BIT-0:
Logic 0 = No data in receive holding register or FIFO.
(normal default condition)
Logic 1 = Data has been received and is saved in the
receive holding register or FIFO.
LSR BIT-1:
Logic 0 = No overrun error. (normal default condition)
Logic 1 = Overrun error. A data overrun error occurred
in the receive shift register. This happens when addi-
tional data arrives while the FIFO is full. In this case
the previous data in the shift register is overwritten.
Note that under this condition the data byte in the
receive shift register is not transferred into the FIFO,
therefore the data in the FIFO is not corrupted by the
error.