ST16C552 Exar Corporation, ST16C552 Datasheet - Page 19

• Manufacturer Part Number: ST16C552
• Description: DUAL UART WITH 16-BYTE FIFO AND PARALLEL PRINTER PORT
• Manufacturer: Exar Corporation

IER BIT 6-7:
Not Used - initialized to a logic 0.
FIFO Control Register (FCR)
This register is used to enable the FIFO’s, clear the
FIFO’s, set the receive FIFO trigger levels, and select
the DMA mode. The DMA, and FIFO modes are
defined as follows:
DMA MODE
single transmit or receive operation, and is similar to
the ST16C450 mode. Transmit Ready (-TXRDY) will
go to a logic 0 when ever an empty transmit space is
available in the Transmit Holding Register (THR).
Receive Ready (-RXRDY) will go to a logic 0 when-
ever the Receive Holding Register (RHR) is loaded
with a character.
mode operation. The transmit interrupt is set when the
transmit FIFO is below the programmed trigger level.
-TXRDY remains a logic 0 as long as one empty FIFO
location is available. The receive interrupt is set when
the receive FIFO fills to the programmed trigger level.
However the FIFO continues to fill regardless of the
programmed level until the FIFO is full. -RXRDY
remains a logic 0 as long as the FIFO fill level is above
the programmed trigger level.
FCR BIT-0:
Logic 0 = Disable the transmit and receive FIFO.
(normal default condition)
Logic 1 = Enable the transmit and receive FIFO. This
bit must be a “1” when other FCR bits are written to or
they will not be programmed.
FCR BIT-1:
Logic 0 = No FIFO receive reset. (normal default
condition)
Logic 1 = Clears the contents of the receive FIFO and
resets the FIFO counter logic (the receive shift regis-
ter is not cleared or altered). This bit will return to a
logic 0 after clearing the FIFO.
Mode 0
Mode 1
Rev. 3.40
Set and enable the interrupt for each
Set and enable the interrupt in a block
19
FCR BIT-2:
Logic 0 = No FIFO transmit reset. (normal default
condition)
Logic 1 = Clears the contents of the transmit FIFO and
resets the FIFO counter logic (the transmit shift regis-
ter is not cleared or altered). This bit will return to a
logic 0 after clearing the FIFO.
FCR BIT-3:
Logic 0 = Set DMA mode “0”. (normal default condi-
tion)
Logic 1 = Set DMA mode “1.”
Transmit operation in mode “0”:
When the 552/552A is in the ST16C450 mode (FIFO’s
disabled, FCR bit-0 = logic 0) or in the FIFO mode
(FIFO’s enabled, FCR bit-0 = logic 1, FCR bit-3 = logic
0) and when there are no characters in the transmit
FIFO or transmit holding register, the -TXRDY pin will
be a logic 0. Once active the -TXRDY pin will go to a
logic 1 after the first character is loaded into the
transmit holding register.
Receive operation in mode “0”:
When the 552/552A is in mode “0” (FCR bit-0 = logic
0) or in the FIFO mode (FCR bit-0 = logic 1, FCR bit-
3 = logic 0) and there is at least one character in the
receive FIFO, the -RXRDY pin will be a logic 0. Once
active the -RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
Transmit operation in mode “1”:
When the 552/552A is in FIFO mode ( FCR bit-0 =
logic 1, FCR bit-3 = logic 1 ), the -TXRDY pin will be
a logic 1 when the transmit FIFO is completely full. It
will be a logic 0 if one or more FIFO locations are
empty.
Receive operation in mode “1”:
When the 552/552A is in FIFO mode (FCR bit-0 = logic
1, FCR bit-3 = logic 1) and the trigger level has been
reached, or a Receive Time Out has occurred, the -
RXRDY pin will go to a logic 0. Once activated, it will
go to a logic 1 after there are no more characters in the
FIFO.
ST16C552/552A