ST16C552 Exar Corporation, ST16C552 Datasheet - Page 18

• Manufacturer Part Number: ST16C552
• Description: DUAL UART WITH 16-BYTE FIFO AND PARALLEL PRINTER PORT
• Manufacturer: Exar Corporation

ST16C552/552A
Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the inter-
rupts from receiver ready, transmitter empty, line
status and modem status registers. These interrupts
would normally be seen on the INT A,B output pins.
IER Vs Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = a logic 1) and
receive interrupts (IER BIT-0 = logic 1) are enabled,
the receive interrupts and register status will reflect
the following:
A) The receive data available interrupts are issued to
the external CPU when the FIFO has reached the
programmed trigger level. It will be cleared when the
FIFO drops below the programmed trigger level.
B) FIFO status will also be reflected in the user
accessible ISR register when the FIFO trigger level is
reached. Both the ISR register status bit and the
interrupt will be cleared when the FIFO drops below
the trigger level.
C) The data ready bit (LSR BIT-0) is set as soon as a
character is transferred from the shift register to the
receive FIFO. It is reset when the FIFO is empty.
IER Vs Receive/Transmit FIFO Polled Mode Op-
eration
When FCR BIT-0 equals a logic 1; resetting IER bits
0-3 enables the 552/552A in the FIFO polled mode of
operation. Since the receiver and transmitter have
separate bits in the LSR either or both can be used in
the polled mode by selecting respective transmit or
receive control bit(s).
A) LSR BIT-0 will be a logic 1 as long as there is one
byte in the receive FIFO.
B) LSR BIT 1-4 will provide the type of errors encoun-
tered, if any.
C) LSR BIT-5 will indicate when the transmit FIFO is
empty.
Rev. 3.40
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D) LSR BIT-6 will indicate when both the transmit
FIFO and transmit shift register are empty.
E) LSR BIT-7 will indicate any FIFO data errors.
IER BIT-0:
This interrupt will be issued when the FIFO has
reached the programmed trigger level or is cleared
when the FIFO drops below the trigger level in the
FIFO mode of operation.
Logic 0 = Disable the receiver ready interrupt. (normal
default condition)
Logic 1 = Enable the receiver ready interrupt.
IER BIT-1:
This interrupt will be issued whenever the THR is
empty and is associated with bit-1 in the LSR register.
Logic 0 = Disable the transmitter empty interrupt.
(normal default condition)
Logic 1 = Enable the transmitter empty interrupt.
IER BIT-2:
This interrupt will be issued whenever a fully as-
sembled receive character is transferred from the
RSR to the RHR/FIFO, i.e., data ready, LSR bit-0.
Logic 0 = Disable the receiver line status interrupt.
(normal default condition)
Logic 1 = Enable the receiver line status interrupt.
IER BIT-3:
Logic 0 = Disable the modem status register interrupt.
(normal default condition)
Logic 1 = Enable the modem status register interrupt.
IER BIT -4:
Not Used - initialized to a logic 0.
IER BIT-5: (ST16C552 only)
Logic 0 = Disable the power down mode. (normal
default condition). The ST16C552A does not support
the power down mode and this bit is set to “0”.
Logic 1 = Enable the power down mode (MCR bit-7
must also be a logic 1 before power down will be
activated).