T436416A TM, T436416A Datasheet - Page 17

• Manufacturer Part Number: T436416A
• Description: 4M X 16 SDRAM
• Manufacturer: TM

tm
Page Read & Write Cycle at Same Bank @ Burst Length = 4
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to
TM Technology Inc. reserves the right
to change products or specifications without notice.
D Q
C L O C K
A 1 0 / A P
A D D R
C K E
R A S
C A S
D Q M
C L = 2
C L = 3
C S
B A
W E
2. Row precharge will interrupt writing. Last data input,
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before
avoid bus contention.
end of burst. Input data after Row precharge cycle will be masked internally.
0
R o w A c t i v e
CH
( A - B n a k )
TE
R a
1
2
t
R C D
3
R e a d ( A -
C a 0
B n a k )
4
5
R e a d ( A -
C b 0
Q a 0
B n a k )
6
Q a 1
Q a 0
7
Q b 0
Q a 1
H I G H
8
* N o t e 1
Q b 1
Q b 0
P.17
9
t
Q b 1
Q b 2
C C D
1 0
1 1
t
RDL
W r i t e ( A -
C c 0
D c 0
D c 0
B n a k )
1 2
before Row precharge, will be written.
D c 1
D c 1
1 3
t
C D L
W r i t e ( A -
C d 0
D d 0
D d 0
B n a k )
1 4
D d 2
D d 1
Publication Date: MAY. 2003
1 5
t
R D L
1 6
P r e c h a r g e
( A - B n a k )
* N o t e 2
* N o t e 3
1 7
T436416A
1 8
Revision: B
: D o n 't c a r e
1 9