T436416A TM, T436416A Datasheet - Page 12

• Manufacturer Part Number: T436416A
• Description: 4M X 16 SDRAM
• Manufacturer: TM

tm
SIMPLIFIED TRUTH TABLE
Notes :
5. During burst read or write with auto precharge , new read/write command cannotbeissued.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
TM Technology Inc. reserves the right
to change products or specifications without notice.
Bank Active & Row Address
Read Column
Address
Write & Column
Address
Burst Stop
Precharge
Clock Suspend or
Active Power Down
Precharge Power Down
Mode
DQM
No Operation Command
1. OP Code : Operation Code. A
2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row
4. BA0~BA1 : Bank select address.
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at
precharge command is meant by ‘Auto’. Auto / self refresh can be issued only at both banks precharge state.
If both BA0 and BA1 are ’Low’ : at read , write , row active and precharge , bank A is selected.
If both BA0 is ‘Low’ and BA1 is ‘High’ : at read , write , row active and precharge , bank B is selected.
If both BA0 is ‘High’ and BA1 is ‘Low’ : at read , write , row active and precharge , bank C is selected.
If both BA0 and BA1 are ’High’ : at read , write , row active and precharge , bank D is selected
If A
Register
Refresh
10
/AP is ‘High’ : at row precharge , BA0 and BA1 ignored and all banks are selected.
COMMAND
CH
TE
Mode Register Set
Auto Refresh
Self
Refresh
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
Both Banks
Entry
Exit
Entry
Exit
Entry
Exit
0
~A
11
CKEn-1 CKEn CS RAS CAS WE DQM
, BA0~BA1 : Program keys.(@MRS)
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
(V=Valid , X=Don’t Care , H=Logic High , L=logic Low)
X
X
X
X
X
X
X
H
H
H
H
L
L
L
P.12
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
t
RP
X
after the end of burst.
H
X
H
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
H
X
H
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
H
H
X
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
V
X
Publication Date: MAY. 2003
BA
0,1
V
V
V
V
X
A
Row Address
10
H
H
H
L
L
L
/AP A
T436416A
X
X
X
X
X
X
X
X
(A0~A7)
(A0~A7)
Column
Address
Column
Address
Revision: B
9
A11
~A
0,
Note
1,2
4,5
4,5
3
3
6
4
7